Optimization of standard cell libraries for low power, high speed, or minimal area designs

2002 ◽  
Author(s):  
C. Fisher ◽  
R. Blankenship ◽  
J. Jensen ◽  
T. Rossman ◽  
K. Svilich
Keyword(s):  
Low Power ◽  
High Speed ◽  
Standard Cell ◽  
Minimal Area

Thermometer to Gray Encoders

2015 ◽  
pp. 323-335
Author(s):  
Yogendra Gupta ◽  
Sandeep Saini
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Gray Code ◽  
Direct Conversion ◽  
Flash Adc ◽  
Analog To Digital ◽  
Modulation Techniques ◽  
On Chip ◽  
Minimal Area

Analog to Digital Converter (ADC) is a key functional block in the design of mixed signal, system on chip, and signal processing applications. An optimized method for the direct conversion of analog signal to Gray code representation is presented. This eliminates the need for binary-to-Gray code conversion in many digital modulation techniques like M-PSK and M-QAM, which uses Gray coding representation to represent the symbols that are modulated. The authors design a low-power and high-speed Thermometer to Gray encoder for Flash ADC, as encoders have been widely utilized in high-performance critical applications which persistently impose special design constraints in terms of high-frequency, low power consumption, and minimal area. In this chapter, they propose a new circuit that converts the Thermometer code to Gray code and also yields minimized power.

High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing

1998 ◽  
Vol 33 (10) ◽  
pp. 1536-1544 ◽  
Author(s):  
K. Koike ◽  
K. Kawai ◽  
A. Onozawa ◽  
Y. Takei ◽  
Y. Kobayashi ◽  
...  
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Design Methodology ◽  
Cell Design ◽  
Standard Cell

HIGH SPEED AND LOW POWER 4*4 ARRAY MULTIPLIER DESIGN

2019 ◽  
Vol 7 (1) ◽  
pp. 24
Author(s):  
N. SURESH ◽  
K. S. SHAJI ◽  
KISHORE REDDY M. CHAITANYA ◽  
◽  
◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Array Multiplier

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

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