A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

New low-power design architecture based on low-swing voltage technique is proposed in this paper. A new CMOS inverter of three output-voltage levels is used to achieve this target. To verify the validity of the proposed technique, three different logic families are used. SPICE simulation results for the three logic families show that more than 45% power dissipation can be saved, without sacrifice the speed operation. Comparison results between the proposed technique and other techniques based on low-swing voltage, shown the superiority of our technique in reducing the power dissipation. Based on 2.4 V supply voltage, a 16 * 16-bit multiplier is implemented by using the proposed technique in 0.25μm silicon technology.

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Low-power design technique for ASICs by partially reducing supply voltage

Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1996.552015 ◽

2002 ◽

Cited By ~ 14

Author(s):

K. Usami ◽

T. Ishikawa ◽

M. Kanazawa ◽

H. Kotani

Keyword(s):

Low Power ◽

Supply Voltage ◽

Low Power Design ◽

Design Technique

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Clustered voltage scaling technique for low-power design

Proceedings of the 1995 international symposium on Low power design - ISLPED '95 ◽

10.1145/224081.224083 ◽

1995 ◽

Cited By ~ 260

Author(s):

Kimiyoshi Usami ◽

Mark Horowitz

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling ◽

Scaling Technique

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Gate Diffusion Input Technique for Power Efficient Circuits and Its Applications

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.b1089.0782s719 ◽

2019 ◽

Vol 8 (2S7) ◽

pp. 472-477

Keyword(s):

Low Power ◽

Digital Circuits ◽

Low Power Design ◽

Design Technique ◽

Power Efficient ◽

Digital Devices ◽

Current State ◽

Cell Modeling ◽

State Of Research

In present scenario world become completely digital. In digital devices the speed and life of the battery is the biggest issue .To resolve these problems there are my techniques for design the devices. A low power design technique is Gate Diffusion input (GDI). This review has the study of GDI technique which is most recent research in low power designing field. In this study many paper were reviewed. The review has structure of THE GDI cell, modeling and application. This review also presented the comparison of GDI technique with other technique of designing. The purpose of the study to find out most recent research in field of GDI. From this study we find out this technique mostly used for digital circuits. This review provides the current state of research and future scopes in this field.

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A Low-Power High-Data-Transmission Multi-Lead ECG Acquisition Sensor System

Sensors ◽

10.3390/s19224996 ◽

2019 ◽

Vol 19 (22) ◽

pp. 4996 ◽

Cited By ~ 5

Author(s):

Liang-Hung Wang ◽

Wei Zhang ◽

Ming-Hui Guan ◽

Su-Ya Jiang ◽

Ming-Hui Fan ◽

...

Keyword(s):

Low Power ◽

Clinical Diagnosis ◽

Medical Staff ◽

Supply Voltage ◽

Sampling Rate ◽

Low Power Design ◽

Sensor System ◽

Acquisition System ◽

Ecg Signal ◽

Acquisition Device

This study presents a low-power multi-lead wearable electrocardiogram (ECG) signal sensor system design that can simultaneously acquire the electrocardiograms from three leads, I, II, and V1. The sensor system includes two parts, an ECG test clothing with five electrode patches and an acquisition device. Compared with the traditional 12-lead wired ECG detection instrument, which limits patient mobility and needs medical staff assistance to acquire the ECG signal, the proposed vest-type ECG acquisition system is very comfortable and easy to use by patients themselves anytime and anywhere, especially for the elderly. The proposed study incorporates three methods to reduce the power consumption of the system by optimizing the micro control unit (MCU) working mode, adjusting the radio frequency (RF) parameters, and compressing the transmitted data. In addition, Huffman lossless coding is used to compress the transmitted data in order to increase the sampling rate of the acquisition system. It makes the whole system operate continuously for a long period of time and acquire abundant ECG information, which is helpful for clinical diagnosis. Finally, a series of tests were performed on the designed wearable ECG device. The results have demonstrated that the multi-lead wearable ECG device can collect, process, and transmit ECG data through Bluetooth technology. The ECG waveforms collected by the device are clear, complete, and can be displayed in real-time on a mobile phone. The sampling rate of the proposed wearable sensor system is 250 Hz per lead, which is dependent on the lossless compression scheme. The device achieves a compression ratio of 2.31. By implementing a low power design on the device, the resulting overall operational current of the device is reduced by 37.6% to 9.87 mA under a supply voltage of 2.1 V. The proposed vest-type multi-lead ECG acquisition device can be easily employed by medical staff for clinical diagnosis and is a suitable wearable device in monitoring and nursing the off-ward patients.

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