AN EFFICIENT LOW-SWING MULTITHRESHOLD-VOLTAGE LOW-POWER DESIGN TECHNIQUE

2004 ◽  
Vol 13 (01) ◽  
pp. 193-203
Author(s):  
A. RJOUB ◽  
M. ALROUSAN ◽  
O. ALJARRAH ◽  
O. KOUFOPAVLOU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Output Voltage ◽  
Supply Voltage ◽  
Low Power Design ◽  
Design Technique ◽  
Cmos Inverter ◽  
Spice Simulation ◽  
Comparison Results ◽  
Simulation Results

New low-power design architecture based on low-swing voltage technique is proposed in this paper. A new CMOS inverter of three output-voltage levels is used to achieve this target. To verify the validity of the proposed technique, three different logic families are used. SPICE simulation results for the three logic families show that more than 45% power dissipation can be saved, without sacrifice the speed operation. Comparison results between the proposed technique and other techniques based on low-swing voltage, shown the superiority of our technique in reducing the power dissipation. Based on 2.4 V supply voltage, a 16 * 16-bit multiplier is implemented by using the proposed technique in 0.25μm silicon technology.

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

2020 ◽  
Vol 10 (4) ◽  
pp. 457-470 ◽  
Author(s):  
Dipanjan Sen ◽  
Savio J. Sengupta ◽  
Swarnil Roy ◽  
Manash Chanda ◽  
Subir K. Sarkar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Dominant Factor ◽  
Double Gate ◽  
Cmos Inverter ◽  
Ultra Low Power ◽  
Voltage Swing

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

scholarly journals Gate Diffusion Input Technique for Power Efficient Circuits and Its Applications

2019 ◽  
Vol 8 (2S7) ◽  
pp. 472-477
Keyword(s):  
Low Power ◽  
Digital Circuits ◽  
Low Power Design ◽  
Design Technique ◽  
Power Efficient ◽  
Digital Devices ◽  
Current State ◽  
Cell Modeling ◽  
State Of Research

In present scenario world become completely digital. In digital devices the speed and life of the battery is the biggest issue .To resolve these problems there are my techniques for design the devices. A low power design technique is Gate Diffusion input (GDI). This review has the study of GDI technique which is most recent research in low power designing field. In this study many paper were reviewed. The review has structure of THE GDI cell, modeling and application. This review also presented the comparison of GDI technique with other technique of designing. The purpose of the study to find out most recent research in field of GDI. From this study we find out this technique mostly used for digital circuits. This review provides the current state of research and future scopes in this field.

scholarly journals Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)

2021 ◽  
Vol 2089 (1) ◽  
pp. 012080
Author(s):  
M. Srinivas ◽  
K.V. Daya Sagar
Keyword(s):  
Energy Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Battery Life

Abstract Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. That is why low power has become a significant factor in CMOS circuit design. The required design and simulation of an AND gate with the BSIM4 MOS parameter model at 27 0C, supply voltage of 0,70V with CMOS technology of 65nm are the validation of the suitability of the proposed circuit technology. AND simulation. The performance parameters for the two AND input gate are compared with the current MTCMOS and SCCMOS techniques, such as sub-threshold leakage power dissipations in active and standby modes, the dynamic dissipation, and propagation period. The proposed hybrid super cutoff complete stack technique compared to the current MTCMOS technology shows a reduction in sub-threshold dissipation power dissipation by 3. 50x and 1.15x in standby modes and active modes respectively. The hybrid surface-cutting technique also shows savings of 2,50 and 1,04 in power dissipation at the sub-threshold in standby modes and active modes compared with the existing SCCMOS Technique.

scholarly journals A Low-Power High-Data-Transmission Multi-Lead ECG Acquisition Sensor System

Sensors ◽  
2019 ◽  
Vol 19 (22) ◽  
pp. 4996 ◽  
Author(s):  
Liang-Hung Wang ◽  
Wei Zhang ◽  
Ming-Hui Guan ◽  
Su-Ya Jiang ◽  
Ming-Hui Fan ◽  
...  
Keyword(s):  
Low Power ◽  
Clinical Diagnosis ◽  
Medical Staff ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Low Power Design ◽  
Sensor System ◽  
Acquisition System ◽  
Ecg Signal ◽  
Acquisition Device

This study presents a low-power multi-lead wearable electrocardiogram (ECG) signal sensor system design that can simultaneously acquire the electrocardiograms from three leads, I, II, and V1. The sensor system includes two parts, an ECG test clothing with five electrode patches and an acquisition device. Compared with the traditional 12-lead wired ECG detection instrument, which limits patient mobility and needs medical staff assistance to acquire the ECG signal, the proposed vest-type ECG acquisition system is very comfortable and easy to use by patients themselves anytime and anywhere, especially for the elderly. The proposed study incorporates three methods to reduce the power consumption of the system by optimizing the micro control unit (MCU) working mode, adjusting the radio frequency (RF) parameters, and compressing the transmitted data. In addition, Huffman lossless coding is used to compress the transmitted data in order to increase the sampling rate of the acquisition system. It makes the whole system operate continuously for a long period of time and acquire abundant ECG information, which is helpful for clinical diagnosis. Finally, a series of tests were performed on the designed wearable ECG device. The results have demonstrated that the multi-lead wearable ECG device can collect, process, and transmit ECG data through Bluetooth technology. The ECG waveforms collected by the device are clear, complete, and can be displayed in real-time on a mobile phone. The sampling rate of the proposed wearable sensor system is 250 Hz per lead, which is dependent on the lossless compression scheme. The device achieves a compression ratio of 2.31. By implementing a low power design on the device, the resulting overall operational current of the device is reduced by 37.6% to 9.87 mA under a supply voltage of 2.1 V. The proposed vest-type multi-lead ECG acquisition device can be easily employed by medical staff for clinical diagnosis and is a suitable wearable device in monitoring and nursing the off-ward patients.

Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

2016 ◽  
Vol 4 (2) ◽  
pp. 333 ◽  
Author(s):  
Kanan Bala Ray ◽  
Sushanta Kumar Mandal ◽  
Shivalal Patro
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Stability ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Power Supply Voltage ◽  
Operation Analysis ◽  
Sram Cell ◽  
Simulation Results

<em>In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell</em>

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