Measurement results of on-chip IR-drop

2003 ◽  
Author(s):  
K. Kobayashi ◽  
J. Yamaguchi ◽  
H. Onodera
Keyword(s):  
Ir Drop ◽  
Measurement Results ◽  
On Chip

Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring

2021 ◽  
Author(s):  
Kazuki Monta ◽  
Leonidas Kataselas ◽  
Ferenc Fodor ◽  
Alkis Hatzopoulos ◽  
Makoto Nagata ◽  
...  
Keyword(s):  
Pattern Generation ◽  
Ir Drop ◽  
On Chip

scholarly journals 0.13 μm CMOS Traveling-Wave Power Amplifier with On- and Off-Chip Gate-Line Termination

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 133
Author(s):  
Aleksandr Vasjanov ◽  
Vaidotas Barzdenas
Keyword(s):  
Optical Communication ◽  
Traveling Wave ◽  
Communication Systems ◽  
Building Blocks ◽  
Power Added Efficiency ◽  
High Data ◽  
Operating Frequency Range ◽  
Measurement Results ◽  
Optical Communication Systems ◽  
On Chip

Broadband amplifiers are essential building blocks used in high data rate wireless, radar, and instrumentation systems, as well as in optical communication systems. Only a traveling-wave amplifier (TWA) provides sufficient bandwidth for broadband applications without reducing modern linearization techniques. TWA requires gate-line and drain-line termination, which can be implemented on- and off-chip. This article compares the performance of identical 0.13 μm CMOS TWAs, differing only in gate-line termination placement. Measurement results revealed that the designed TWAs with on- and off-chip termination have a bandwidth of 10 GHz with a maximum gain of 15 dB and a power-added efficiency (PAE) of 5%–22% in the whole operating frequency range. Placing the gate-line termination off-chip results in an S21 flatness reduction, compared to the gain of a TWA with on-chip termination. Gain fluctuation over frequency is reduced by 4–8 dB when the termination resistor is placed as an external circuit.

scholarly journals TRO: An On-Chip Ring Oscillator-Based GHz Transient IR-Drop Monitor

2017 ◽  
Vol 36 (5) ◽  
pp. 855-868 ◽  
Author(s):  
Xiaoxiao Wang ◽  
Pengyuan Jiao ◽  
Mehdi Sadi ◽  
Donglin Su ◽  
LeRoy Winemberg ◽  
...  
Keyword(s):  
Ring Oscillator ◽  
Ir Drop ◽  
On Chip

Countermeasures against physical security attacks on ICs utilizing on-chip wideband ADCs

2022 ◽  
Author(s):  
Takuji Miki ◽  
Makoto Nagata
Keyword(s):  
Active Fault ◽  
Fault Injection ◽  
Side Channel ◽  
Security Attacks ◽  
Input Buffer ◽  
Analog To Digital ◽  
Side Channel Analysis ◽  
Measurement Results ◽  
Channel Analysis ◽  
On Chip

Abstract Cryptographic ICs on edge devices for internet-of-things (IoT) applications are exposed to an adversary and threatened by malicious side channel analysis. On-chip analog monitoring by sensor circuits embedded inside the chips is one of the possible countermeasures against such attacks. An on-chip monitor circuit consisting of a successive approximation register (SAR) analog-to-digital converter (ADC) and an input buffer acquires a wideband signal, which enables to detects an irregular noise due to an active fault injection and a passive side channel leakage analysis. In this paper, several countermeasures against security attacks utilizing wideband on-chip monitors are reviewed. Each technique is implemented on a prototype chip, and the measurement results prove they can effectively detect and diagnose the security attacks.

On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links

2012 ◽  
Vol 3 (4) ◽  
pp. 42-56 ◽  
Author(s):  
Sebastian Höppner ◽  
Dennis Walter ◽  
Georg Ellguth ◽  
René Schüffny
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Error Rates ◽  
Oxide Semiconductor ◽  
Multiprocessor System ◽  
Semiconductor Technology ◽  
Clock Jitter ◽  
Measurement Results ◽  
Delay Variations ◽  
On Chip

This paper presents techniques for measurement and compensation of timing variations in clock and data channels of source-synchronous high-speed serial network-on-chip (NoC) links. Timing mismatch measurements are performed by means of asynchronous sub-sampling. This allows the use of low quality sampling clocks to reduce test hardware overhead for integration into complex MPSoCs (Multiprocessor System-on-Chip) with multiple NoC links. The effect of clock jitter on the measurement results is evaluated. Delay mismatch is compensated by tunable delay cells. The proposed technique enables compensation of delay variations to realize high-speed NoC links with sufficient yield. It is demonstrated at NoC links as part of an MPSoC in 65 nm Complementary Metal Oxide Semiconductor technology, where the calibration significantly reduces bit-error-rates of a 72 GBit/s (8 GBit/s per lane) link over 4 mm on-chip interconnect.

An on-chip test structure to measure the Seebeck coefficient of thermopile sensors

2021 ◽  
Author(s):  
Peng Huang ◽  
Jianyu Fu ◽  
Yihong Lu ◽  
Jinbiao Liu ◽  
Jian Zhang ◽  
...  
Keyword(s):  
Seebeck Coefficient ◽  
Thermal Parameter ◽  
Test Structure ◽  
Sensitive Region ◽  
Wide Range ◽  
Temperature Detector ◽  
Measurement Results ◽  
On Chip ◽  
Thermopile Sensor

Abstract Thermopile sensors have a wide range of applications in consumer and industry. Seebeck coefficient is a basic thermal parameter of thermopile sensors. Extracting the Seebeck coefficient of both materials and thermocouple in thermopile sensors is of great importance. In this work, an on-chip test structure is designed. It consists of a substrate, a framework, supporting legs and a sensitive region which has a resistor serving as both heater and temperature detector. A set of on-chip test structures are fabricated along with a thermopile sensor. Its measurement results are analyzed and compared with apparatus measurement results. These results are consistent with each other, and the validity of structure is verified.

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