Validity of compact gate C — V model on SiC-SiO2 MOS device

2012 ◽  
Author(s):  
Chaitali Chakraborty
Keyword(s):  
Mos Device

Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications

2007 ◽  
Vol 84 (12) ◽  
pp. 2916-2920 ◽  
Author(s):  
Chang-Ta Yang ◽  
Kuei-Shu Chang-Liao ◽  
Hsin-Chun Chang ◽  
B.S. Sahu ◽  
Tzu-Chen Wang ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Metal Gate ◽  
Device Applications ◽  
Mos Device

The influence of electron beam energy on defect density in MOS device quality oxides

Vacuum ◽  
1988 ◽  
Vol 38 (11) ◽  
pp. 1041-1043 ◽  
Author(s):  
A Balasiński ◽  
A Jakubowski ◽  
A Świt
Keyword(s):  
Electron Beam ◽  
Beam Energy ◽  
Defect Density ◽  
Electron Beam Energy ◽  
Mos Device

Influences of MOS Device Characteristic under Different Oxygen-Dose Participations in the Silicon Substrate

2015 ◽  
Vol 656-657 ◽  
pp. 8-13
Author(s):  
Shen Li Chen ◽  
Tsung Shiung Lee ◽  
Yu Ting Huang
Keyword(s):  
Silicon Substrate ◽  
Czochralski Method ◽  
Silicon Substrates ◽  
Trap Charge ◽  
Substrate Quality ◽  
Mos Devices ◽  
Starting Point ◽  
Charge Characteristic ◽  
Mos Device

A silicon substrate is the starting point of producing the semiconductor component, so that the quality of semiconductor substrate is very important during the VLSI fabrication. In this paper, we will evaluate the influence of MOS device characteristics under different oxygen impurities in silicon substrates. In the course of silicon substrate pulling process by Czochralski method, the defect and impurity will be existed; the oxygen atom will be induced substrate dislocations and affected the substrate quality. In this work, different oxygen doses will be used in wafer to study the impacts on MOS CV curve characteristic, interface trap charge characteristic, ID-VDScurve, ID-VGScurve, and threshold voltage behaviors of MOS devices.

Optimised Multi-Scan H-Beam Annealing Of Mos Devices

1981 ◽  
Vol 4 ◽  
Author(s):  
C J Pollard ◽  
A E Glaccum ◽  
J D Speight
Keyword(s):  
Low Dose ◽  
Gate Dielectrics ◽  
Mos Devices ◽  
Device Processing ◽  
H Beam ◽  
Mos Gate ◽  
Mos Device

ABSTRACTThe optimum e-beam anneal conditions for damage free wafer annealing, implant activation uniformity across 3 inch wafers and low dose boron activation have been investigated with reference to the needs of MOS device processing. Some effects of e-beam annealing on MOS gate dielectrics are reported.

MOS Device Fabrication Using X‐Ray Lithography

1981 ◽  
Vol 128 (11) ◽  
pp. 2434-2437 ◽  
Author(s):  
K. Suzuki ◽  
J. Matsui ◽  
T. Ono ◽  
Y. Saito
Keyword(s):  
Device Fabrication ◽  
X Ray ◽  
Mos Device
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