scholarly journals Fuzzy Based Adaptive Controller for on - Chip Communication

2018 ◽  
Vol 7 (3.27) ◽  
pp. 362
Author(s):  
M Jasmin ◽  
T Vigneswaran
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Error Detection ◽  
Input Data ◽  
Fuzzy Controller ◽  
Proper Time ◽  
System On Chip ◽  
Coding Scheme ◽  
Error Detection And Correction ◽  
On Chip

Occurrence of bit error is more when communication takes place in System on chip environment. By employing proper error detection and correction codes the bit error rate can be considerably reduced in On-chip communication. As System on chip involves heterogeneous system the efficiency of communication is improved when reconfigurable multiple coding schemes are preferred. Depending upon the requirements for various subsystem the correct code has to be selected. Due to the variations in input demands based on various subsystems the proper selection of codes become fuzzy in nature. In this paper Fuzzy Controller is designed to select the correct coding scheme. Inputs are given to the fuzzy controller based on the application demand of the user. The input parameters are minimum bit error rate, computational complexity and correlation level of the input data. Fuzzy Controller employs three membership functions and 27 rules to select the appropriate coding scheme. The selected coding scheme should be communicated at the proper time to the decoder. To enable the decoding process selected coding scheme is communicated effectively by using less overhead frame format. To verify the functionality of fuzzy controller random input data sets are used for testing.  

Desain dan Simulasi Encoder-Decoder Berbasis Angka Sembilan Untuk Transmisi Informasi Digital

2015 ◽  
Vol 6 (3) ◽  
Author(s):  
Bobby Yuhanda ◽  
Nasaruddin Nasaruddin ◽  
Syahrial Syahrial
Keyword(s):  
Computer Simulation ◽  
Bit Error Rate ◽  
Error Rate ◽  
Error Detection ◽  
Communication Channel ◽  
Multipath Fading ◽  
Digital Information ◽  
Coding Scheme ◽  
Error Detection And Correction ◽  
Information And Communication

Abstract. The development of information and communication technology is growing rapidly, particularly in the transmission of digital information. The process of transmitting digital information through the communication channel will be interferenced by noise, distortion and multipath fading so that the information is likely to experience an error or incorrect detection at the receiver, which can decrease the system performance. This research proposes the design and simulation of encoder-decoder based on the number nine to transmit digital information reliably and precisely. The goal of this research is to design and simulate the encoder decoder as a scheme of error detection and correction and to reduce bit error rate that occurs during the process of transmitting digital information. The research method uses design and computer simulation where the encoder-decoder is modeled mathematically, design is structured and a computer simulation is developed for the performance of encoder-decoder based on the number nine in the transmission of digital information. The result of this research shows that the proposed encoder-decoder can detect the errors transmission and correct the errors at receiver.Keywords: Digital information, encoder-decoder, coding scheme, and transmission information. Abstrak. Perkembangan teknologi komunikasi dan informasi saat ini sangat pesat, khususnya dalam teknologi transmisi informasi digital. Proses transmisi informasi digital melalui kanal komunikasi akan mendapat gangguan seperti noise, distorsi, interferensi dan multipath fading. Sehingga informasi yang dikirim kemungkinan akan terjadi kesalahan atau salah deteksi pada penerima, yang menyebabkan penurunan kinerja dari sistem. Penelitian ini mengusulkan suatu desain dan simulasi encoder-decoder berbasis angka sembilan untuk transmisi informasi digital, yang mampu bekerja secara handal dan tepat. Adapun tujuan penelitian ini adalah untuk merancang dan mensimulasikan encoder-decoder berbasis angka Sembilan sebagai skema deteksi dan koreksi kesalahan serta mengurangi bit error rate yang terjadi pada saat proses transmisi informasi digital. Metode penelitian yang digunakan adalah perancangan dan simulasi komputer, dimana prosesnya adalah pemodelan secara matematis, perancangan encoder-decoder, pembuatan simulasi kinerja encoder-decoder berbasis angka sembilan untuk transmisi informasi digital. Hasil penelitian ini menunjukan bahwa encoder-decoder yang diusulkan dapat mendeteksi kesalahan transmisi dan mengoreksi kesalahan pada penerima.Kata Kunci: Informasi digital, encoder-decoder, pengkodean kanal, transmisi informasi.

scholarly journals Performance Enhancement of MIMO-OFDM using Redundant Residue Number System

2018 ◽  
Vol 8 (5) ◽  
pp. 3902
Author(s):  
M. I. Youssef ◽  
A. E. Emam ◽  
M. Abd Elghany
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Error Detection ◽  
Orthogonal Frequency Division Multiplexing ◽  
Number System ◽  
Residue Number System ◽  
Error Detection And Correction ◽  
Residue Number ◽  
Mimo Ofdm ◽  
Redundant Residue Number System

Telecommunication industry requires high capacity networks with high data rates which are achieved through utilization of Multiple-Input-Multiple-Output (MIMO) communication along with Orthogonal Frequency Division Multiplexing (OFDM) system. Still, the communication channel suffers from noise, interference or distortion due to hardware design limitations, and channel environment, and to combat these challenges, and achieve enhanced performance; various error control techniques are implemented to enable the receiver to detect any possible received errors and correct it and thus; for a certain transmitted signal power the system would have lower Bit Error Rate (BER). The provided research focuses on Redundant Residue Number System (RRNS) coding as a Forward Error Correction (FEC) scheme that improves the performance of MIMO-OFDM based wireless communications in comparison with current methods as Low-Density Parity Check (LDPC) coders at the transmitter side or equalizers at receiver side. The Bit Error Rate (BER) performance over the system was measured using MATLAB tool for different simulated channel conditions, including the effect of signal amplitude reduction and multipath delay spreading. Simulation results had shown that RRNS coding scheme provides an enhancement in system performance over conventional error detection and correction coding schemes by utilizing the distinct features of Residue Number System (RNS).

Hamming Product Code Based Multiple Bit Error Correction Coding Scheme Using Keyboard Scan Based Decoding for on Chip Interconnects Links

2012 ◽  
Vol 241-244 ◽  
pp. 2457-2461 ◽  
Author(s):  
Murali Maheswari ◽  
Gopalakrishnan Seetharaman
Keyword(s):  
Error Correction ◽  
Error Rate ◽  
Iterative Decoding ◽  
Error Control ◽  
Low Complexity ◽  
Hardware Complexity ◽  
Error Correction Coding ◽  
Product Code ◽  
Coding Scheme ◽  
On Chip

In this paper, we present multiple bit error correction coding scheme using extended Hamming product code combined with type II HARQ and keyboard scan based error flipping to correct multiple bit errors for on chip interconnect. The keyboard scan based error flipping reduces the hardware complexity of the decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 86% of reduction in area and 23% of reduction in decoder delay with only small increase in residual flit error rate compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 66% of links power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.

First Experimental Bit-Error-Rate Validation of 12.5-Gb/s Silicon Modulator Enabling Photonic Networks-on-Chip

2010 ◽  
Author(s):  
Aleksandr Biberman ◽  
Noam Ophir ◽  
Keren Bergman ◽  
Sasikanth Manipatruni ◽  
Long Chen ◽  
...  
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Photonic Networks ◽  
Networks On Chip ◽  
On Chip ◽  
Silicon Modulator

scholarly journals Error Detection in Turbo Decoding using Neural Network

2019 ◽  
Vol 9 (1S) ◽  
pp. 218-221
Keyword(s):  
Neural Network ◽  
Bit Error Rate ◽  
Error Rate ◽  
Error Detection ◽  
Turbo Codes ◽  
Iterative Decoding ◽  
Turbo Decoding ◽  
Turbo Decoder ◽  
The Neural Network ◽  
Turbo Encoder

In this paper reduction of errors in turbo decoding is done using neural network. Turbo codes was one of the first thriving attempt for obtaining error correcting performance in the vicinity of the theoretical Shannon bound of –1.6 db. Parallel concatenated encoding and iterative decoding are the two techniques available for constructing turbo codes. Decrease in Eb/No necessary to get a desired bit-error rate (BER) is achieved for every iteration in turbo decoding. But the improvement in Eb/No decreases for each iteration. From the turbo encoder, the output is taken and this is added with noise, when transmitting through the channel. The noisy data is fed as an input to the neural network. The neural network is trained for getting the desired target. The desired target is the encoded data. The turbo decoder decodes the output of neural network. The neural network help to reduce the number of errors. Bit error rate of turbo decoder trained using neural network is less than the bit error rate of turbo decoder without training.

scholarly journals A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders

Information ◽  
2019 ◽  
Vol 10 (4) ◽  
pp. 151
Author(s):  
Gabriele Meoni ◽  
Gianluca Giuffrida ◽  
Luca Fanucci
Keyword(s):  
High Throughput ◽  
Network Topology ◽  
Bit Error Rate ◽  
Error Rate ◽  
Field Programmable Gate Array ◽  
Input Data ◽  
Telecommunication Systems ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Convolutional Encoders

During the last years, recursive systematic convolutional (RSC) encoders have found application in modern telecommunication systems to reduce the bit error rate (BER). In view of the necessity of increasing the throughput of such applications, several approaches using hardware implementations of RSC encoders were explored. In this paper, we propose a hardware intellectual property (IP) for high throughput RSC encoders. The IP core exploits a methodology based on the ABCD matrices model which permits to increase the number of inputs bits processed in parallel. Through an analysis of the proposed network topology and by exploiting data relative to the implementation on Zynq 7000 xc7z010clg400-1 field programmable gate array (FPGA), an estimation of the dependency of the input data rate and of the source occupation on the parallelism degree is performed. Such analysis, together with the BER curves, provides a description of the principal merit parameters of a RSC encoder.

RELIABILITY OF ERROR CORRECTING CODES ON WIRELESS INFORMATION NETWORKS

1996 ◽  
Vol 03 (04) ◽  
pp. 283-304
Author(s):  
MARTIN L. SHOOMAN ◽  
FRANK A. CASSARA
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
System Performance ◽  
Communication Systems ◽  
System Analysis ◽  
Error Correcting Codes ◽  
Information Networks ◽  
Coding Scheme ◽  
Data Rates ◽  
Study Results

Error correcting codes are well known techniques for improving bit error rate (BER) performance in digital communication systems and are particularly important in wireless information networks to help establish reliable communication links. This paper examines the effect of coder/decoder circuitry failures on the overall communication system performance. A system analysis of the error correction coding scheme performance must include an evaluation of the reliability of the coder/decoder circuitry because their failures also serve as a source of undetected errors. The parity bit code, Hamming single error correcting and detecting code, and the Reed–Solomon code are included in the study. Results reveal that for applications as described in the text that require low bit error rate and operate at low data rates, the reliability of the coding circuitry can play a significant role in determining overall system performance. In fact, for such error and data rates, a simpler coding scheme with higher circuit reliability may actually be more beneficial than a more complex coding scheme with enhanced error correcting ability but with a higher chip failure rate.

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