Chip-to-chip communication by optical routing inside a thin glass substrate

Author(s):  
Lars Brusberg ◽  
Norbert Schlepple ◽  
Henning Schroder
2013 ◽  
Vol 79 (6) ◽  
pp. 559-564 ◽  
Author(s):  
Naoki OIWA ◽  
Tomoko HIRAYAMA ◽  
Takashi MATSUOKA ◽  
Hiroshi YABE

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001893-001917 ◽  
Author(s):  
Yu-Hua Chen ◽  
Yu-Chung Hsieh ◽  
Wei-Di Lin ◽  
Chun-Hsien Chien ◽  
Dyi-Chung Hu

Although Silicon interposer has good performance, however high cost is still the major issue and limits its high volume adoption. Therefore to decrease the assembly cost or develop low cost, high density interconnect interposer technology is the keys to enable 2.5D SiP integration. One possibility is to develop low cost interposer by adopting the alternative materials instead of Silicon. The glass, low CTE polymer material, ceramic, etc. may be included. Glass represents an attractive choice with potential of tailorable properties dependent on specific glass composition. By targeting the coefficient of thermal expansion (CTE), the CTE of glass can be made to match perfectly with silicon dies and for reliable package. In addition, the advantages of using glass for interposer derive from process flexibility for size and thickness since the glass fusion process provides sheets with dimensions of more than three meters. It is straight forward to provide glass substrate of almost any size needed. Large glass panels are ideally suited for fabrication of interposer where the panel process is expected to provide large number of interposers in each run compared with wafer processing. Additionally, the two sided processing of the panel, the avoidance of Si wafer CMP processes further enable lower unit cost for the interposer Consequently, glass is an ideal interposer material due to its insulating property, large panel size availability, high modulus and ability to tailor CTE. In this paper, we successfully demonstrate manufacturing feasibility of glass substrate with 4 build-up layers starting with a thin glass panel in 508mm×508mm panel size format and under the IC substrate manufacturing environment. Glass thickness of 100~300um could be processed through the IC substrate HVM line. The laser via in via or direct metallization technology could be selected for double side electrical connection. The copper line width/space of 8/8um was demonstrated by current substrate HVM line. By adopting advanced lithography process and material, line width/space less than 2/2um was achievable. TCT Reliability test without glass crack results will also be discussed.


2009 ◽  
Vol 40 (1) ◽  
pp. 1324
Author(s):  
Boaz Nishri ◽  
Svetlana Brodetski ◽  
Arie Harnik ◽  
Marc Delorme
Keyword(s):  

Coatings ◽  
2019 ◽  
Vol 9 (3) ◽  
pp. 183 ◽  
Author(s):  
Guobin Jia ◽  
Jonathan Plentz ◽  
Jan Dellith ◽  
Andrea Dellith ◽  
Ruri Wahyuono ◽  
...  

Graphene and its derivatives have many superior electrical, thermal, mechanical, chemical, and structural properties, and promise for many applications. One of the issues for scalable applications is the lack of a simple, reliable method that allows the deposit of a well-ordered monolayer using low-cost graphene flakes onto target substrates with different surface properties. Another issue is the adhesion of the deposited graphene thin film, which has not been well investigated yet. Following our former finding of a double self-assembly (DSA) process for efficient deposition of a monolayer of graphene flakes (MGFs), in this work we demonstrate that the DSA process can be applied even on very challenging samples including highly hydrophobic polytetrafluoroethylene (PTFE), flexible textiles, complex 3D objects, and thin glass fibers. Additionally, we tested adhesion of the graphene flakes on the flat glass substrate by scotch tape peel test of the MGFs. The results show that the graphene flakes adhere quite well on the flat glass substrate and most of the graphene flakes stay on the glass. These findings may trigger many large-scale applications of low-cost graphene feedstocks and other 2D materials.


2015 ◽  
Author(s):  
Sho Itoh ◽  
Masaaki Sakakura ◽  
Yasuhiko Shimotsuma ◽  
Kiyotaka Miura

Author(s):  
Scott McCann ◽  
Vanessa Smet ◽  
Venky Sundaram ◽  
Rao R. Tummala ◽  
Suresh K. Sitaraman

2011 ◽  
Vol 42 (1) ◽  
pp. 652-654 ◽  
Author(s):  
Suresh T. Gulati ◽  
Jamie Westbrook ◽  
Stephen Carley ◽  
Hemanth Vepakomma ◽  
Toshihiko Ono
Keyword(s):  

Author(s):  
Yoshitaro Sakata ◽  
Nao TERASAKI

Abstract Demand for flexible electronics is increasing due to recent global movements related to IoT. In particular, the ultra-thin glass substrate can be bent, its use is expanding for various applications such as thin liquid crystal panels. On the other hand, fine-polishing techniques such as chemical mechanical polishing treatments, are important techniques in glass substrate manufacturing. However, these techniques may cause microcracks under the surface of glass substrates because they use mechanical friction. We propose a novel non-contact thermal stress-induced light-scattering method (N-SILSM) using a heating device for inspecting surfaces to detect polishing-induced microcracks. In this report, we carry out the selective detection of microcracks and tiny particles using a N-SILSM with temperature variation. Our results show that microcracks and tiny particles can be distinguished and measured by a N-SILSM utilizing temperature change, and that microcrack size can be estimated based on the change in light-scattering intensity.


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