Design and fabrication of low-loss horizontal and vertical interconnect links using air-clad transmission lines and through silicon vias

Author(s):  
Rohit Sharma ◽  
Erdal Uzunlar ◽  
Vachan Kumar ◽  
Rajarshi Saha ◽  
Xinyi Yeow ◽  
...  
2021 ◽  
Vol 238 ◽  
pp. 111509
Author(s):  
Shuxiao Wang ◽  
Qing Wang ◽  
Yufei Liu ◽  
Lianxi Jia ◽  
Mingbin Yu ◽  
...  

2016 ◽  
Vol 26 (3) ◽  
pp. 168-170 ◽  
Author(s):  
Hanju Oh ◽  
Paragkumar A. Thadesar ◽  
Gary S. May ◽  
Muhannad S. Bakir

2016 ◽  
Vol 58 ◽  
pp. 83-88 ◽  
Author(s):  
Jinrong Su ◽  
Runbo Ma ◽  
Xinwei Chen ◽  
Liping Han ◽  
Rongcao Yang ◽  
...  

2016 ◽  
Vol 149 ◽  
pp. 145-152 ◽  
Author(s):  
Xin Sun ◽  
Runiu Fang ◽  
Yunhui Zhu ◽  
Xiao Zhong ◽  
Yuan Bian ◽  
...  

Author(s):  
Ingrid De Wolf ◽  
Ahmad Khaled ◽  
Martin Herms ◽  
Matthias Wagner ◽  
Tatjana Djuric ◽  
...  

Abstract This paper discusses the application of two different techniques for failure analysis of Cu through-silicon vias (TSVs), used in 3D stacked-IC technology. The first technique is GHz Scanning Acoustic Microscopy (GHz- SAM), which not only allows detection of defects like voids, cracks and delamination, but also the visualization of Rayleigh waves. GHz-SAM can provide information on voids, delamination and possibly stress near the TSVs. The second is a reflection-based photoelastic technique (SIREX), which is shown to be very sensitive to stress anisotropy in the Si near TSVs and as such also to any defect affecting this stress, such as delamination and large voids.


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