<p>Power management in integrated circuits is critical and some
ICs require voltages to be applied in a particular sequence. Integrated
circuits consist of various distinct sub-circuits and power delivery to each of
those circuits at the proper time is required for proper operation. Some
examples are Subscriber line interface circuit (SLIC), switching voltage
regulators, etc. Thus, startup delay circuits are necessary as they ensure the
delivery of power to circuits at the appropriate time. Time delays are conventionally
generated by resistor-capacitor pair but the time constant is very small, for
higher time delay, we have to increase resistor-capacitor sizes which require
more space and is not economical. In this paper, a new technique is proposed
for the generation of sufficient time delays eliminating the need for larger
resistor and capacitor combination. The proposed startup delay circuit is
designed in 180 nm. CMOS process and simulated in LTSpice.</p>
Modified Startup Delay Providing Circuit for Integrated Circuits