scholarly journals Modified Startup Delay Providing Circuit for Integrated Circuits

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Integrated Circuits ◽  
Time Delays ◽  
Proper Time ◽  
Power Delivery ◽  
Voltage Regulators ◽  
Cmos Process ◽  
Interface Circuit ◽  
Startup Delay ◽  
A New Technique ◽  
Proper Operation

<p>Power management in integrated circuits is critical and some ICs require voltages to be applied in a particular sequence. Integrated circuits consist of various distinct sub-circuits and power delivery to each of those circuits at the proper time is required for proper operation. Some examples are Subscriber line interface circuit (SLIC), switching voltage regulators, etc. Thus, startup delay circuits are necessary as they ensure the delivery of power to circuits at the appropriate time. Time delays are conventionally generated by resistor-capacitor pair but the time constant is very small, for higher time delay, we have to increase resistor-capacitor sizes which require more space and is not economical. In this paper, a new technique is proposed for the generation of sufficient time delays eliminating the need for larger resistor and capacitor combination. The proposed startup delay circuit is designed in 180 nm. CMOS process and simulated in LTSpice.</p>

scholarly journals Modified Startup Delay Providing Circuit for Integrated Circuits

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Integrated Circuits ◽  
Time Delays ◽  
Proper Time ◽  
Power Delivery ◽  
Voltage Regulators ◽  
Cmos Process ◽  
Interface Circuit ◽  
Startup Delay ◽  
A New Technique ◽  
Proper Operation

<p>Power management in integrated circuits is critical and some ICs require voltages to be applied in a particular sequence. Integrated circuits consist of various distinct sub-circuits and power delivery to each of those circuits at the proper time is required for proper operation. Some examples are Subscriber line interface circuit (SLIC), switching voltage regulators, etc. Thus, startup delay circuits are necessary as they ensure the delivery of power to circuits at the appropriate time. Time delays are conventionally generated by resistor-capacitor pair but the time constant is very small, for higher time delay, we have to increase resistor-capacitor sizes which require more space and is not economical. In this paper, a new technique is proposed for the generation of sufficient time delays eliminating the need for larger resistor and capacitor combination. The proposed startup delay circuit is designed in 180 nm. CMOS process and simulated in LTSpice.</p>

scholarly journals Optimization of spaceflight millimeter-wave impedance matching networks using laser trimming

2021 ◽  
pp. 1-7
Author(s):  
K. Parow-Souchon ◽  
D. Cuadrado-Calle ◽  
S. Rea ◽  
M. Henry ◽  
M. Merritt ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Millimeter Wave ◽  
Impedance Matching ◽  
Wave Impedance ◽  
Low Noise ◽  
Device Performance ◽  
Interface Circuits ◽  
Interface Circuit ◽  
Noise Amplifier

Abstract Realizing packaged state-of-the-art performance of monolithic microwave integrated circuits (MMICs) operating at millimeter wavelengths presents significant challenges in terms of electrical interface circuitry and physical construction. For instance, even with the aid of modern electromagnetic simulation tools, modeling the interaction between the MMIC and its package embedding circuit can lack the necessary precision to achieve optimum device performance. Physical implementation also introduces inaccuracies and requires iterative interface component substitution that can produce variable results, is invasive and risks damaging the MMIC. This paper describes a novel method for in situ optimization of packaged millimeter-wave devices using a pulsed ultraviolet laser to remove pre-selected areas of interface circuit metallization. The method was successfully demonstrated through the optimization of a 183 GHz low noise amplifier destined for use on the MetOp-SG meteorological satellite series. An improvement in amplifier output return loss from an average of 12.9 dB to 22.7 dB was achieved across an operational frequency range of 175–191 GHz and the improved circuit reproduced. We believe that our in situ tuning technique can be applied more widely to planar millimeter-wave interface circuits that are critical in achieving optimum device performance.

Development of Backside Buried Metal Layer Technology for 3D-ICs

2019 ◽  
Vol 2019 (1) ◽  
pp. 000268-000273
Author(s):  
Naoya Watanabe ◽  
Yuuki Araga ◽  
Haruo Shimamoto ◽  
Katsuya Kikuchi ◽  
Makoto Nagata
Keyword(s):  
Integrated Circuits ◽  
Metal Layer ◽  
Three Dimensional ◽  
Chip Thickness ◽  
Power Delivery ◽  
Silicon Structure ◽  
Metal Insulator ◽  
3D Ics ◽  
Power Delivery Network ◽  
Global Power

Abstract In this study, we developed backside buried metal (BBM) layer technology for three-dimensional integrated circuits (3D-ICs). In this technology, a BBM layer for global power routing is introduced in the large vacant area on the backside of each chip and is parallelly connected with the frontside routing of the chip. The resistances of the power supply (VDD) and ground (VSS) lines consequently decrease. In addition, the BBM structure acts as a decoupling capacitor because it is buried in the Si substrate and has metal–insulator–silicon structure. Therefore, the impedance of power delivery network can be reduced by introducing the BBM layer. The fabrication process of the BBM layer for 3D-ICs was simple and compatible with the via-last through-silicon via (TSV) process. With this process, it was possible to fabricate the BBM layer consisting of electroplated Cu (thickness: approximately 10 μm) buried in the backside of the CMOS chip (thickness: 43 μm), which was connected with the frontside routing of the chip using 9 μm-diameter TSVs.

Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Logic Synthesis ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Timing Models ◽  
High Temperature Operation

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

scholarly journals Biodismantling, a Novel Application of Bioleaching in Recycling of Electronic Wastes

Recycling ◽  
2020 ◽  
Vol 5 (3) ◽  
pp. 22
Author(s):  
Benjamin Monneron-Enaud ◽  
Oliver Wiche ◽  
Michael Schlömann
Keyword(s):  
Integrated Circuits ◽  
Printed Circuit Boards ◽  
Raw Materials ◽  
Iron Sulfate ◽  
Circuit Boards ◽  
Copper Leaching ◽  
Valuable Metals ◽  
A New Technique ◽  
Abiotic Controls ◽  
Processing Steps

Electronic components (EC) from waste electrical and electronic equipment (WEEE) such as resistors, capacitors, diodes and integrated circuits are a subassembly of printed circuit boards (PCB). They contain a variety of economically valuable elements e.g., tantalum, palladium, gold, and rare earth elements. However, until recently there has been no systematic dismantling and recycling of the EC to satisfy the demand for raw materials. A problem connected with the recycling of the EC is the removal of the components (dismantling) in order to recover the elements in later processing steps. The aim of the present study was to develop a new technique of dismantling using bioleaching technology to lower costs and environmental impact. In triplicate batch experiments, used PCBs were treated by bioleaching using an iron-oxidizing mixed culture largely dominated by Acidithiobacillus ferrooxidans strains supplemented with 20 mM ferrous iron sulfate at pH 1.8 and 30 °C for 20 days. Abiotic controls were treated by similar conditions in two different variations: 20 mM of Fe2+ and 15 mM of Fe3+. After 20 days, successful dismantling was obtained in both the bioleaching and the Fe3+ control batch. The control with Fe2+ did not show a significant effect. The bioleaching condition presented a lower rate of dismantling which can partially be explained by a constantly higher redox potential leading to a competition of solder leaching and copper leaching from the printed copper wires. The results showed that biodismantling—dismantling using bioleaching—is possible and can be a new unit operation of the recycling process to maximize the recovery of valuable metals from PCBs.

Design of Conductive MWNTs/SiO2 Humidity Sensor Interface ASIC Based on AC Signals

2013 ◽  
Vol 562-565 ◽  
pp. 344-349
Author(s):  
Tuo Li ◽  
Xiao Wei Liu ◽  
Liang Yin ◽  
Chang Chun Dong
Keyword(s):  
Humidity Sensor ◽  
Work Group ◽  
High Sensitivity ◽  
Cmos Process ◽  
Humidity Sensing ◽  
Interface Circuit ◽  
Testing Frequency ◽  
Zero Offset ◽  
Different Response ◽  
Circuit Output

Previous research on MWNTs/SiO2 humidity sensing film by our work group has proved that MWNTs sensor has a different response mechanism to humidity at AC testing signals and shows greater testing stability and higher sensitivity, compared with traditional DC signal measurement. An interface circuit for conductive MWNTs/SiO2 humidity sensor is designed in this paper for humidity detection and prospection in miniaturization and integration. It aims at detecting the sensor’s humidity sensitive conductance signal at AC testing signals, and inhibiting the interference of capacitance signals. The ASIC demodulates the two signals by their phase difference and outputs a direct voltage proportional to conductance. The layout for ASIC is drawn by standard 0.5um P2M2 CMOS process and has a total area of 4*2mm2. In circuit level simulation by HSPICE which introduces practical data of the sensor’s humidity sensing characteristics, the relation of circuit output to conductance turns out to have great linearity at no more than 300 kHz and zero offset can be neglected at less than 100 kHz frequency. It is feasible to select proper testing frequency for high sensitivity and stability and make further investigations on the sensor’s frequency property.

FEATURES OF THE TECHNOLOGICAL PROCESS OF MANUFACTURING SPACE-BASED MICROCHIPS USING CMOS KNS TECHNOLOGY

2020 ◽  
Vol 13 (3) ◽  
pp. 53-58
Author(s):  
Vladimir Zolnikov ◽  
Svetlana Evdokimova ◽  
Irina ZHuravlyeva ◽  
Elena Maklakova ◽  
Anna Ilunina
Keyword(s):  
Integrated Circuits ◽  
Technological Process ◽  
Cmos Integrated Circuits ◽  
Cmos Process

The article deals with the technological process of manufacturing CMOS integrated circuits on KNS (silicon on sapphire) structures for space purposes. The technology is based on an n-type CMOS process with one level of polysilicon and two levels of metal. The components of the technological process are analyzed. The sequence of the technological process and its features are given. An example of a description of one of the elements is considered.

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