Novel Approach to Design DPL-based Ternary Logic Circuits

Author(s):  
Narendra Deo Singh ◽  
Rakesh Kumar Singh ◽  
Rahul Raj ◽  
Shivam Jyoti ◽  
Aloke Saha
Small ◽  
2021 ◽  
pp. 2103365
Author(s):  
Chungryeol Lee ◽  
Junhwan Choi ◽  
Hongkeun Park ◽  
Changhyeon Lee ◽  
Chang‐Hyun Kim ◽  
...  

2020 ◽  
Vol 30 (15) ◽  
pp. 2050222
Author(s):  
Li Luo ◽  
Zhekang Dong ◽  
Xiaofang Hu ◽  
Lidan Wang ◽  
Shukai Duan

The nanoscale implementations of ternary logic circuits are particularly attractive because of high information density and operation speed that can be achieved by using emerging memristor technologies. Memristor is a nanoscale device with nonvolatility and adjustable multilevel states, which creates an intriguing opportunity for the implementation of ternary logic operations. This paper proposes a novel memristor-based design for stateful ternary logic, including AND, OR, NOT, NAND, NOR, and COPY operations. In the proposed memristor ternary logic (MTL) design, the resistance of memristor is the only logic state variable for representing the input and output. By sensing the value of the input memristors, the resistance of the output memristor changes accordingly. Furthermore, the MTL gates are not only capable of performing logic operations, but also storing logic values. To illustrate the potential of the methodology, a single-input-three-output ternary decoder is designed by using the proposed ternary logic circuits. Simulation results verify the effectiveness of the presented design.


1990 ◽  
Vol 137 (1) ◽  
pp. 21 ◽  
Author(s):  
X.W. Wu ◽  
F.P. Prosser
Keyword(s):  

Author(s):  
Sepher Tabrizchi ◽  
Fazel Sharifi ◽  
Abdel-Hameed A. Badawy

Traditional silicon binary circuits continue to face challenges such as high leakage power dissipation and large area of interconnections. Multiple-Valued Logic (MVL) and nano-devices are two feasible solutions to overcome these problems. In this paper, we present a novel method to design ternary logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs). The proposed designs use the unique properties of CNFETs, e.g., adjusting the Carbon Nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility of P-FET and N-FET transistors. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state which saves power while the circuits are not in use. We show a more detailed application of our approach by designing a two-digit adder-subtractor circuit. We simulate the proposed ternary circuits using HSPICE via standard 32nm CNFET technology. The simulation results indicate the correct operation of the designs under different process, voltage and temperature (PVT) variations. Moreover, we designed a two-digit adder/subtractor and a power efficient ternary logic ALU based on the proposed gates. Simulation results show that the two-digit adder/subtractor using our proposed gates has 12X and 5X lower power consumption and PDP (power delay product) respectively, compared to previous designs.


Sign in / Sign up

Export Citation Format

Share Document