Self-checking binary logic systems using ternary logic circuits

1984 ◽  
Vol 9 (3) ◽  
pp. 100-104 ◽  
Author(s):  
M. Hu ◽  
K. C. Smith
Keyword(s):  
Logic Circuits ◽  
Ternary Logic ◽  
Binary Logic ◽  
Logic Systems

scholarly journals Design and Implementation of Ternary Logic Circuits for VLSI Applications

2020 ◽  
Vol 9 (4) ◽  
pp. 3117-3121
Keyword(s):  
Power Dissipation ◽  
Digital Circuits ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Combinational Circuits ◽  
Ternary Logic ◽  
Binary Logic ◽  
Design And Implementation ◽  
Half Adder

This paper mainly concentrates on the design and implementation of ternary logic circuits. The ternary numeral system has its base as 3. Ternary logic will use three symbols, which are, 0,1 and 2. The ternary logic has significant merits over binary logic in designing digital circuits. In this paper, it is proposed to implement a half adder circuit using ternary 3 to 1 multiplexer. The main objective of the work is, to design and implement ternary logic circuits and to analyse the function of the ternary combinational circuits using mentor graphics tool in 90nm technology. This paper also compares the ternary half adder design using k-map method with the proposed ternary half adder using multiplexer in terms of power dissipation, propagation delay and transistor count

scholarly journals Design of a High Performance 4-Bit Ternary Multiplier using CNTFET

2019 ◽  
Vol 9 (2) ◽  
pp. 3106-3111
Keyword(s):  
High Performance ◽  
Field Effect Transistors ◽  
Logic Circuits ◽  
Ternary Logic ◽  
Chip Area ◽  
Binary Logic ◽  
Digital World ◽  
Multiple Valued Logic ◽  
Carbon Nano Tubes ◽  
Carbon Nano Tube

In digital world, digital circuits are influenced by binary logic. Ternary logic which follows the multiple valued logic concept for designing the logic circuits which is an great alternate to the normal binary logic due to its less power consumption and chip area is reduces. Carbon Nano-tube Field-Effect Transistors (CNTFET) is selected to implement the ternary logic circuits due to its mechanical , electrical and thermal properties. The unique feature of CNTFETs has the potential of getting required threshold voltage by varying the diameter of carbon nano-tubes that makes them as a best appropriate type for implementing the ternary logic. In this paper a 4-Bit Ternary Multiplier is designed using 1-Bit ternary multiplier by CNTFET 32nm technology node and simulated in Hspice tool. The proposed 1-Bit multiplier has 10% less delay and 18% less power than the 1-Bit multiplier proposed by Srivasu et al.

Novel Approach to Design DPL-based Ternary Logic Circuits

2018 ◽  
Author(s):  
Narendra Deo Singh ◽  
Rakesh Kumar Singh ◽  
Rahul Raj ◽  
Shivam Jyoti ◽  
Aloke Saha
Keyword(s):  
Logic Circuits ◽  
Ternary Logic ◽  
Novel Approach

A Universal Method for Designing Multi-Digit Ternary to Binary Converter Using CNTFET

2020 ◽  
Vol 29 (12) ◽  
pp. 2050196 ◽  
Author(s):  
Maryam Shahangian ◽  
Seied Ali Hosseini ◽  
Reza Faghih Mirzaee
Keyword(s):  
Threshold Voltage ◽  
High Efficiency ◽  
Field Effect Transistors ◽  
Block Diagram ◽  
Universal Method ◽  
Ternary Logic ◽  
Chip Area ◽  
Binary Logic ◽  
Multiple Valued Logic ◽  
Essential Components

Ternary logic can reduce the number of interconnections, chip area and power dissipation. In addition, one of the important features of carbon nanotube field effect transistors (CNTFETs) is the capability of adjusting threshold voltage. As a result, the design complexity of ternary circuits can be decreased. The structure of a mixed radix system which is based on multi-valued and binary logic is more appropriate compared to only multiple-valued logic (MVL). Therefore, ternary-to-binary and binary-to-ternary converters are the essential components for the ternary signaling on the bus and the binary logic processing circuits. It is also important for the creation of compatibility between the binary and ternary logic. This study is about a multi-digit binary-to-ternary converter by using CNTFET. At first, the algorithm used for the multi-digit conversion from ternary to binary logic is addressed in this paper. Then, the paper proposes a block diagram suitable for designing the multi-digit ternary-to-binary converter. Some new gates including One-Active Gate and Two-Active Gate, as well as two types of binary half-and full-adders, are designed for the purpose of implementing the proposed block diagram. This is done by adjusting the proper threshold voltage for CNTFETs. The proposed algorithm can also be applied to any desired number of bits. The proper operation and high efficiency of the proposed converter are confirmed by HSPICE simulation results and 32[Formula: see text]nm CNTFET technology from the Stanford University.

Systematic Control of Negative Transconductance in Organic Heterojunction Transistor for High‐Performance, Low‐Power Flexible Ternary Logic Circuits

Small ◽  
2021 ◽  
pp. 2103365
Author(s):  
Chungryeol Lee ◽  
Junhwan Choi ◽  
Hongkeun Park ◽  
Changhyeon Lee ◽  
Chang‐Hyun Kim ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Logic Circuits ◽  
Ternary Logic ◽  
Systematic Control ◽  
Heterojunction Transistor

MTL: Memristor Ternary Logic Design

2020 ◽  
Vol 30 (15) ◽  
pp. 2050222
Author(s):  
Li Luo ◽  
Zhekang Dong ◽  
Xiaofang Hu ◽  
Lidan Wang ◽  
Shukai Duan
Keyword(s):  
Logic Circuits ◽  
Logic Design ◽  
Ternary Logic ◽  
Nanoscale Device ◽  
State Variable ◽  
Operation Speed ◽  
Input And Output ◽  
Single Input ◽  
Logic Operations ◽  
High Information

The nanoscale implementations of ternary logic circuits are particularly attractive because of high information density and operation speed that can be achieved by using emerging memristor technologies. Memristor is a nanoscale device with nonvolatility and adjustable multilevel states, which creates an intriguing opportunity for the implementation of ternary logic operations. This paper proposes a novel memristor-based design for stateful ternary logic, including AND, OR, NOT, NAND, NOR, and COPY operations. In the proposed memristor ternary logic (MTL) design, the resistance of memristor is the only logic state variable for representing the input and output. By sensing the value of the input memristors, the resistance of the output memristor changes accordingly. Furthermore, the MTL gates are not only capable of performing logic operations, but also storing logic values. To illustrate the potential of the methodology, a single-input-three-output ternary decoder is designed by using the proposed ternary logic circuits. Simulation results verify the effectiveness of the presented design.

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