scholarly journals Energy Efficient Tri-State CNFET Ternary Logic Gates

Author(s):  
Sepher Tabrizchi ◽  
Fazel Sharifi ◽  
Abdel-Hameed A. Badawy

Traditional silicon binary circuits continue to face challenges such as high leakage power dissipation and large area of interconnections. Multiple-Valued Logic (MVL) and nano-devices are two feasible solutions to overcome these problems. In this paper, we present a novel method to design ternary logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs). The proposed designs use the unique properties of CNFETs, e.g., adjusting the Carbon Nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility of P-FET and N-FET transistors. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state which saves power while the circuits are not in use. We show a more detailed application of our approach by designing a two-digit adder-subtractor circuit. We simulate the proposed ternary circuits using HSPICE via standard 32nm CNFET technology. The simulation results indicate the correct operation of the designs under different process, voltage and temperature (PVT) variations. Moreover, we designed a two-digit adder/subtractor and a power efficient ternary logic ALU based on the proposed gates. Simulation results show that the two-digit adder/subtractor using our proposed gates has 12X and 5X lower power consumption and PDP (power delay product) respectively, compared to previous designs.

ACS Nano ◽  
2012 ◽  
Vol 6 (5) ◽  
pp. 4013-4019 ◽  
Author(s):  
Li Ding ◽  
Zhiyong Zhang ◽  
Tian Pei ◽  
Shibo Liang ◽  
Sheng Wang ◽  
...  

2019 ◽  
Author(s):  
Sarah Guiziou ◽  
Guillaume Perution-Kihli ◽  
Federico Ulliana ◽  
Michel Leclere ◽  
Jerome Bonnet

Logic circuits operating in living cells are generally built by mimicking electronic layouts, and scale-up is accomplished using additional layers of elementary logic gates like NOT and NOR gates. Recombinase-based logic, in which logic is implemented using DNA inversion or excision, allows for highly efficient, compact and single-layer design architectures. However, recombinase logic architectures depart from electronic design principles, and gate design performed empirically is challenging for an increasing number of inputs. Here we used a combinatorial approach to explore the design space of recombinase logic devices. We generated combinations and permutations of recombination sites, genes, and regulatory elements, for a total of ~19 million designs supporting the implementation of all 2- and 3-input logic functions and up to 92% of 4-input logic functions. We estimated the influence of different design constraints on the number of executable functions, and found that the use of DNA inversion and transcriptional terminators were key factors to implement the vast majority of logic functions. We provide a user-friendly interface, called RECOMBINATOR (http://recombinator.lirmm.fr/index.php), that enable users to navigate the design space of recombinase-based logic, find architectures implementing a specific logic function and sort them according to various biological criteria. Finally, we define a set of 16 architectures from which all 256 3-input logic functions can be derived. This work provides a theoretical foundation for the systematic exploration and design of single-layer recombinase logic devices.


Science ◽  
2020 ◽  
Vol 368 (6493) ◽  
pp. 878-881 ◽  
Author(s):  
Mengyu Zhao ◽  
Yahong Chen ◽  
Kexin Wang ◽  
Zhaoxuan Zhang ◽  
Jason K. Streit ◽  
...  

Biofabricated semiconductor arrays exhibit smaller channel pitches than those created using existing lithographic methods. However, the metal ions within biolattices and the submicrometer dimensions of typical biotemplates result in both poor transport performance and a lack of large-area array uniformity. Using DNA-templated parallel carbon nanotube (CNT) arrays as model systems, we developed a rinsing-after-fixing approach to improve the key transport performance metrics by more than a factor of 10 compared with those of previous biotemplated field-effect transistors. We also used spatially confined placement of assembled CNT arrays within polymethyl methacrylate cavities to demonstrate centimeter-scale alignment. At the interface of high-performance electronics and biomolecular self-assembly, such approaches may enable the production of scalable biotemplated electronics that are sensitive to local biological environments.


IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 104701-104717 ◽  
Author(s):  
Furqan Zahoor ◽  
Tun Zainal Azni Zulkifli ◽  
Farooq Ahmad Khanday ◽  
Sohiful Anuar Zainol Murad

2017 ◽  
Vol 46 ◽  
pp. 82-92 ◽  
Author(s):  
Saleh Safapour ◽  
Reza Sabbaghi-Nadooshan ◽  
Ali Asghar Shokri

Molecular electronics seeks to decrease the cost, power consumption and size of devices, using a variety of approaches. However, few attempts have been made to address circuit simulation. The availability of common semiconductor components means they can be used for modeling and simulating molecular circuits to speed progress in molecular electronics. The present study examines the switching of a gated oligo-phenylenevinylene (OPV) molecule as a NMOS molecular transistor, resistance as an indicator of methyl molecules, and the linking of these abilities using LTspice simulation software. The circuit simulation of molecules of basic logic gates, half-adder, full-adder, and multiplier logic circuits are carried out. The numerical results may shed light on the next applications of molecular systems and make them a good, promising candidate for field-effect transistors.


2020 ◽  
Vol 11 (1) ◽  
Author(s):  
Erjuan Guo ◽  
Zhongbin Wu ◽  
Ghader Darbandy ◽  
Shen Xing ◽  
Shu-Jen Wang ◽  
...  

Abstract The main advantage of organic transistors with dual gates/bases is that the threshold voltages can be set as a function of the applied second gate/base bias, which is crucial for the application in logic gates and integrated circuits. However, incorporating a dual gate/base structure into an ultra-short channel vertical architecture represents a substantial challenge. Here, we realize a device concept of vertical organic permeable dual-base transistors, where the dual base electrodes can be used to tune the threshold voltages and change the on-currents. The detailed operation mechanisms are investigated by calibrated TCAD simulations. Finally, power-efficient logic circuits, e.g. inverter, NAND/AND computation functions are demonstrated with one single device operating at supply voltages of <2.0 V. We believe that this work offers a compact and technologically simple hardware platform with excellent application potential for vertical-channel organic transistors in complex logic circuits.


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