Active Device Performance after Fan-out Wafer-level Packaging Process

Author(s):  
Hong-Yu Li ◽  
Masaya Kawano ◽  
Simon Lim ◽  
Daniel Ismael Cereno ◽  
Vasarla Nagendra Sekhar
2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Che-Jung Chang ◽  
Der-Chiang Li ◽  
Wen-Li Dai ◽  
Chien-Chih Chen

The wafer-level packaging process is an important technology used in semiconductor manufacturing, and how to effectively control this manufacturing system is thus an important issue for packaging firms. One way to aid in this process is to use a forecasting tool. However, the number of observations collected in the early stages of this process is usually too few to use with traditional forecasting techniques, and thus inaccurate results are obtained. One potential solution to this problem is the use of grey system theory, with its feature of small dataset modeling. This study thus uses the AGM(1,1) grey model to solve the problem of forecasting in the pilot run stage of the packaging process. The experimental results show that the grey approach is an appropriate and effective forecasting tool for use with small datasets and that it can be applied to improve the wafer-level packaging process.


2021 ◽  
Vol 21 (5) ◽  
pp. 2987-2991
Author(s):  
Geumtaek Kim ◽  
Daeil Kwon

Along with the reduction in semiconductor chip size and enhanced performance of electronic devices, high input/output density is a desired factor in the electronics industry. To satisfy the high input/output density, fan-out wafer-level packaging has attracted significant attention. While fan-out wafer-level packaging has several advantages, such as lower thickness and better thermal resistance, warpage is one of the major challenges of the fan-out wafer-level packaging process to be minimized. There have been many studies investigating the effects of material properties and package design on warpage using finite element analysis. Current warpage simulations using finite element analysis have been routinely conducted with deterministic input parameters, although the parameter values are uncertain from the manufacturing point of view. This assumption may lead to a gap between the simulation and the field results. This paper presents an uncertainty analysis of wafer warpage in fan-out wafer-level packaging by using finite element analysis. Coefficient of thermal expansion of silicon is considered as a parameter with uncertainty. The warpage and the von Mises stress are calculated and compared with and without uncertainty.


2000 ◽  
Author(s):  
Rahul Kapoor ◽  
Swee Y. Khim ◽  
Goh H. Hwa

2003 ◽  
Vol 782 ◽  
Author(s):  
V. Dragoi ◽  
P. Lindner ◽  
T. Glinsner ◽  
M. Wimplinger ◽  
S. Farrens

ABSTRACTAnodic bonding is a powerful technique used in MEMS manufacturing. This process is applied mainly for building three-dimensional structures for microfluidic applications or for wafer level packaging. Process conditions will be evaluated in present paper. An experimental solution for bonding three wafers in one single process step (“triple-stack bonding”) will be introduced.


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