Low-cost wafer level packaging process

2000 ◽  
Author(s):  
Rahul Kapoor ◽  
Swee Y. Khim ◽  
Goh H. Hwa
Keyword(s):  
Low Cost ◽  
Wafer Level ◽  
Packaging Process ◽  
Wafer Level Packaging

scholarly journals Utilizing an Adaptive Grey Model for Short-Term Time Series Forecasting: A Case Study of Wafer-Level Packaging

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Che-Jung Chang ◽  
Der-Chiang Li ◽  
Wen-Li Dai ◽  
Chien-Chih Chen
Keyword(s):  
Semiconductor Manufacturing ◽  
Manufacturing System ◽  
Grey System Theory ◽  
Grey Model ◽  
Grey System ◽  
Wafer Level ◽  
Short Term ◽  
Packaging Process ◽  
Wafer Level Packaging

The wafer-level packaging process is an important technology used in semiconductor manufacturing, and how to effectively control this manufacturing system is thus an important issue for packaging firms. One way to aid in this process is to use a forecasting tool. However, the number of observations collected in the early stages of this process is usually too few to use with traditional forecasting techniques, and thus inaccurate results are obtained. One potential solution to this problem is the use of grey system theory, with its feature of small dataset modeling. This study thus uses the AGM(1,1) grey model to solve the problem of forecasting in the pilot run stage of the packaging process. The experimental results show that the grey approach is an appropriate and effective forecasting tool for use with small datasets and that it can be applied to improve the wafer-level packaging process.

Warpage Simulation During Fan-Out Wafer-Level Packaging Process with Uncertainty of Material Properties

2021 ◽  
Vol 21 (5) ◽  
pp. 2987-2991
Author(s):  
Geumtaek Kim ◽  
Daeil Kwon
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Material Properties ◽  
Coefficient Of Thermal Expansion ◽  
Input Output ◽  
Wafer Level ◽  
High Input ◽  
Element Analysis ◽  
Packaging Process ◽  
Wafer Level Packaging

Along with the reduction in semiconductor chip size and enhanced performance of electronic devices, high input/output density is a desired factor in the electronics industry. To satisfy the high input/output density, fan-out wafer-level packaging has attracted significant attention. While fan-out wafer-level packaging has several advantages, such as lower thickness and better thermal resistance, warpage is one of the major challenges of the fan-out wafer-level packaging process to be minimized. There have been many studies investigating the effects of material properties and package design on warpage using finite element analysis. Current warpage simulations using finite element analysis have been routinely conducted with deterministic input parameters, although the parameter values are uncertain from the manufacturing point of view. This assumption may lead to a gap between the simulation and the field results. This paper presents an uncertainty analysis of wafer warpage in fan-out wafer-level packaging by using finite element analysis. Coefficient of thermal expansion of silicon is considered as a parameter with uncertainty. The warpage and the von Mises stress are calculated and compared with and without uncertainty.

Characterization of a Semiconductor Packaging System utilizing Through Glass Via (TGV) Technology

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001378-001407
Author(s):  
Tim Mobley ◽  
Roupen Keusseyan ◽  
Tim LeClair ◽  
Konstantin Yamnitskiy ◽  
Regi Nocon
Keyword(s):  
Low Cost ◽  
Glass Wafer ◽  
Wafer Level ◽  
Packaging System ◽  
Thin Glass ◽  
Wafer Level Packaging ◽  
Recent Developments ◽  
And Performance ◽  
New Generation ◽  
Semiconductor Packaging

Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging. This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specifications required for through glass vias (TGV's). Creating redistribution layers (RDL) or circuit layers on both sides of large thin glass wafer poses several challenges, which this paper will discuss, as well as, performance and reliability of the circuit layers on TGV wafers or substrates. Additionally, there are glass-to-glass welding techniques that can be utilized in conjunction with TGV wafers with RDL, which provide ambient glass-to-glass attachments of lids and standoffs, which do not outgas during thermal cycle and allow the semiconductor devices to be attached first without having to reflow at lower temperatures. Fabrication challenges, reliability testing results, and performance of this semiconductor packaging system will be discussed in this paper.

Innovative 3D Structures Utilizing Wafer Level Fan-Out (WLFO) Technology

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001486-001519
Author(s):  
Curtis Zwenger ◽  
JinYoung Khim ◽  
YoonJoo Khim ◽  
SeWoong Cha ◽  
SeungJae Lee ◽  
...  
Keyword(s):  
Low Cost ◽  
Ease Of Use ◽  
Wafer Level ◽  
3D Structures ◽  
Wafer Level Packaging ◽  
Functional Convergence ◽  
3D Packaging ◽  
Improved Design ◽  
On Chip ◽  
Mobile Handset

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need, such as Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP). In particular, the emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Wafer Level Fan-Out is a package technology designed to provide increased I/O density within a reduced footprint and profile for low density single & multi-die applications at a lower cost. The improved design capability of WLFO is due, in part, to the fine feature capabilities associated with wafer level packaging. This can allow much more aggressive design rules to be applied compared to competing laminate-based technologies. In addition, the unique characteristics of WLFO enable innovative 3D structures to be created that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of WLFO and its extension into unique 3D structures. In addition, the advantages of these WLFO designs will be reviewed in comparison to current competing packaging technologies. Process & material characterization, design simulation, and reliability data will be presented to show how WLFO is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products.

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Active Device Performance after Fan-out Wafer-level Packaging Process

2018 ◽  
Author(s):  
Hong-Yu Li ◽  
Masaya Kawano ◽  
Simon Lim ◽  
Daniel Ismael Cereno ◽  
Vasarla Nagendra Sekhar
Keyword(s):  
Device Performance ◽  
Wafer Level ◽  
Active Device ◽  
Packaging Process ◽  
Wafer Level Packaging

scholarly journals Design and Fabrication of Wafer-Level Microlens Array with Moth-Eye Antireflective Nanostructures

Nanomaterials ◽  
2019 ◽  
Vol 9 (5) ◽  
pp. 747 ◽  
Author(s):  
Shuping Xie ◽  
Xinjun Wan ◽  
Bo Yang ◽  
Wei Zhang ◽  
Xiaoxiao Wei ◽  
...  
Keyword(s):  
Nanoimprint Lithography ◽  
Production Efficiency ◽  
Low Cost ◽  
Microlens Array ◽  
Wafer Level ◽  
Lens Array ◽  
Wafer Level Packaging ◽  
High Production ◽  
Aspherical Lenses ◽  
Profile Accuracy

Wafer-level packaging (WLP) based camera module production has attracted widespread industrial interest because it offers high production efficiency and compact modules. However, suppressing the surface Fresnel reflection losses is challenging for wafer-level microlens arrays. Traditional dielectric antireflection (AR) coatings can cause wafer warpage and coating fractures during wafer lens coating and reflow. In this paper, we present the fabrication of a multiscale functional structure-based wafer-level lens array incorporating moth-eye nanostructures for AR effects, hundred-micrometer-level aspherical lenses for camera imaging, and a wafer-level substrate for wafer assembly. The proposed fabrication process includes manufacturing a wafer lens array metal mold using ultraprecise machining, chemically generating a nanopore array layer, and replicating the multiscale wafer lens array using ultraviolet nanoimprint lithography. A 50-mm-diameter wafer lens array is fabricated containing 437 accurate aspherical microlenses with diameters of 1.0 mm; each lens surface possesses nanostructures with an average period of ~120 nm. The microlens quality is sufficient for imaging in terms of profile accuracy and roughness. Compared to lenses without AR nanostructures, the transmittance of the fabricated multiscale lens is increased by ~3% under wavelengths of 400–750 nm. This research provides a foundation for the high-throughput and low-cost industrial application of wafer-level arrays with AR nanostructures.

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