Advanced Anodic Bonding Processes For MEMS Applications

2003 ◽  
Vol 782 ◽  
Author(s):  
V. Dragoi ◽  
P. Lindner ◽  
T. Glinsner ◽  
M. Wimplinger ◽  
S. Farrens
Keyword(s):  
Three Dimensional ◽  
Anodic Bonding ◽  
Process Conditions ◽  
Wafer Level ◽  
Process Step ◽  
Packaging Process ◽  
Powerful Technique ◽  
Wafer Level Packaging ◽  
Single Process ◽  
Single Process Step

ABSTRACTAnodic bonding is a powerful technique used in MEMS manufacturing. This process is applied mainly for building three-dimensional structures for microfluidic applications or for wafer level packaging. Process conditions will be evaluated in present paper. An experimental solution for bonding three wafers in one single process step (“triple-stack bonding”) will be introduced.

scholarly journals Utilizing an Adaptive Grey Model for Short-Term Time Series Forecasting: A Case Study of Wafer-Level Packaging

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Che-Jung Chang ◽  
Der-Chiang Li ◽  
Wen-Li Dai ◽  
Chien-Chih Chen
Keyword(s):  
Semiconductor Manufacturing ◽  
Manufacturing System ◽  
Grey System Theory ◽  
Grey Model ◽  
Grey System ◽  
Wafer Level ◽  
Short Term ◽  
Packaging Process ◽  
Wafer Level Packaging

The wafer-level packaging process is an important technology used in semiconductor manufacturing, and how to effectively control this manufacturing system is thus an important issue for packaging firms. One way to aid in this process is to use a forecasting tool. However, the number of observations collected in the early stages of this process is usually too few to use with traditional forecasting techniques, and thus inaccurate results are obtained. One potential solution to this problem is the use of grey system theory, with its feature of small dataset modeling. This study thus uses the AGM(1,1) grey model to solve the problem of forecasting in the pilot run stage of the packaging process. The experimental results show that the grey approach is an appropriate and effective forecasting tool for use with small datasets and that it can be applied to improve the wafer-level packaging process.

Application of Tem on Sub-Half Micron Semiconductor Devices

1998 ◽  
Vol 523 ◽  
Author(s):  
Hong Zhang
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Failure Analysis ◽  
Process Evaluation ◽  
Semiconductor Devices ◽  
Single Source ◽  
Process Step ◽  
Transmission Electron ◽  
Single Process ◽  
Single Process Step

AbstractApplication of transmission electron microscopy on sub-half micron devices has been illustrated in terms of process evaluation and failure analysis. For process evaluation, it is emphasized that a large number of features need to be examined in order to have reliable conclusions about the processes, while for failure analysis, the goal is to pin-point a single process step causing failure or a single source introducing the particle defect.

Wafer Level Micropackaging of MEMS Devices Using Thin Film Anodic Bonding

2002 ◽  
Vol 729 ◽  
Author(s):  
Lauren E. S. Rohwer ◽  
Andrew D. Oliver ◽  
Melissa V. Collins
Keyword(s):  
Shear Strength ◽  
Test Sample ◽  
Anodic Bonding ◽  
Mems Devices ◽  
Wafer Level ◽  
Thermal Actuators ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Leak Testing ◽  
Before And After

AbstractA wafer level packaging technique that involves anodic bonding of Pyrex wafers to released surface micromachined wafers is demonstrated. Besides providing a hermetic seal, this technique allows full wafer release, provides protection during die separation, and offers the possibility of integration with optoelectronic devices. Anodic bonding was performed under applied voltages up to 1000 V, and temperatures ranging from 280 to 400°C under vacuum (10-4Torr). The quality of the bonded interfaces was evaluated using shear strength testing and leak testing. The shear strength of Pyrex-to-polysilicon and aluminum bonds was ∼10-15 MPa. The functionality of surface micromachined polysilicon devices was tested before and after anodic bonding. 100% of thermal actuators, 94% of torsional ratcheting actuators, and 70% of microengines functioned after bonding. The 70% yield was calculated from a test sample of 25 devices.

Warpage Simulation During Fan-Out Wafer-Level Packaging Process with Uncertainty of Material Properties

2021 ◽  
Vol 21 (5) ◽  
pp. 2987-2991
Author(s):  
Geumtaek Kim ◽  
Daeil Kwon
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Material Properties ◽  
Coefficient Of Thermal Expansion ◽  
Input Output ◽  
Wafer Level ◽  
High Input ◽  
Element Analysis ◽  
Packaging Process ◽  
Wafer Level Packaging

Along with the reduction in semiconductor chip size and enhanced performance of electronic devices, high input/output density is a desired factor in the electronics industry. To satisfy the high input/output density, fan-out wafer-level packaging has attracted significant attention. While fan-out wafer-level packaging has several advantages, such as lower thickness and better thermal resistance, warpage is one of the major challenges of the fan-out wafer-level packaging process to be minimized. There have been many studies investigating the effects of material properties and package design on warpage using finite element analysis. Current warpage simulations using finite element analysis have been routinely conducted with deterministic input parameters, although the parameter values are uncertain from the manufacturing point of view. This assumption may lead to a gap between the simulation and the field results. This paper presents an uncertainty analysis of wafer warpage in fan-out wafer-level packaging by using finite element analysis. Coefficient of thermal expansion of silicon is considered as a parameter with uncertainty. The warpage and the von Mises stress are calculated and compared with and without uncertainty.

Upscaling panel size for Cu plating on FOPLP (Fan Out Panel Level Packaging) applications to reduce manufacturing cost

2018 ◽  
Vol 2018 (1) ◽  
pp. 000037-000042
Author(s):  
Henning Hübner ◽  
Christian Ohde ◽  
Dirk Ruess
Keyword(s):  
Large Scale ◽  
Metal Deposition ◽  
Process Conditions ◽  
Manufacturing Cost ◽  
Wafer Level ◽  
Process Technology ◽  
Process Step ◽  
Glass Substrates ◽  
Component Design ◽  
Advanced Packaging

Abstract Electrolytic metal deposition is a key process step in the manufacturing of vertical and horizontal interconnections used in today's PCBs and IC substrates on one hand and advanced packaging applications on the other hand. Historically both application areas were clearly defined and separated by different requirements in feature sizes and substrate formats. PCBs and IC substrates were based on organic large scale substrates with rather large features while advanced packaging technology is wafer based with the capability to incorporate fine features down to a few microns. The ever increasing demand of higher performance, lower cost and thinner end user devices like smartphones require intense developments and innovation in all areas of the electronic component design including the substrate and chip packaging. Latest manufacturing technologies in both areas like fan-out wafer level packaging and advanced substrates are constantly emerging and promise to be a critical piece to meet these requirements. As a consequence both areas are currently merging while creating a new application segment. This segment combines the request of small feature sizes with the manufacturability on large scale substrates. Obviously many of the traditional process technologies like plating and available equipment cannot be easily adopted and need certain developments, adaptions and improvements. In this respect, a key challenge in the area of electrolytic metal deposition is the combination of various challenging requirements: creation of feature sizes down to 2μm L/S with heterogeneous feature density on large substrates up to 600mm at excellent metal thickness uniformity and high plating speed. The paper presents latest studies and conclusions in critical performance areas of the plating process such as electrolyte fluid dynamics, impact of anode design, pulse reverse rectification and newly designed electrolytes. Finally latest test results of optimized process conditions will be discussed in detail with different feature sizes providing data of within die and within substrate uniformity. All tests are done on panel level, both organic and glass substrates. The latest findings and achievements of the discussed panel based plating process technology will support the industry to develop panel based packaging processes that meet both technical and commercial requirements.

A numerical study on mitigation of flying dies in compression molding of microelectronic packages

2018 ◽  
Vol 2018 (1) ◽  
pp. 000355-000360
Author(s):  
Marc Dreissigacker ◽  
Ole Hoelck ◽  
Joerg Bauer ◽  
Tanja Braun ◽  
Karl-Friedrich Becker ◽  
...  
Keyword(s):  
Numerical Study ◽  
Compression Molding ◽  
Packaging Material ◽  
Process Conditions ◽  
Microelectronic Packaging ◽  
Wafer Level ◽  
Temperature Dependent ◽  
Wafer Level Packaging ◽  
Compression Speed ◽  
Complex Manner

Abstract Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds (EMC) depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dies during encapsulation in Fan-Out Wafer Level Packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemo-rheology, as well as to extract forces exerted on individual dies. It offers separate evaluation of pressure and shear-contributions for two cases, 0 ° and 45 ° between the dies' frontal area and the melt front. Process parameters, such as compression speed and process temperature, are determined to minimize flying dies and thereby maximize yield. The approach is easily scalable and is therefore well suited to face the challenges that come with the current efforts towards the transition from FOWLP to FOPLP (Fan-Out Panel Level Packaging).

Damascene-Patterned Metal-Adhesive (Cu-BCB) Redistribution Layers

2006 ◽  
Vol 970 ◽  
Author(s):  
Ronald J. Gutmann ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu
Keyword(s):  
Bonding Strength ◽  
Adhesive Bonding ◽  
Process Integration ◽  
Three Dimensional ◽  
Adhesive Layer ◽  
Wafer Level ◽  
Technology Platform ◽  
Metal Bonding ◽  
Wafer Level Packaging ◽  
Metal Metal

ABSTRACTA monolithic, wafer-level three-dimensional (3D) technology platform is described that is compatible with next-generation wafer level packaging (WLP) processes. The platform combines the advantages of both (1) high bonding strength and adaptability to IC wafer topography variations with spin-on dielectric adhesive bonding and (2) process integration and via-area advantages of metal-metal bonding. A copper-benzocyclobutene (Cu-BCB) process is described that incorporates single-level damascene-patterned Cu vias with partially-cured BCB as the bonding adhesive layer. A demonstration vehicle consisting of a two-wafer stack of 2-4 μm diameter vias has shown the bondability of both Cu-to-Cu and BCB-to-BCB. Planarization conditions to achieve BCB-BCB bonding with low-resistance Cu-Cu contacts have been examined, with wafer-scale planarization requirements compared to other 3D platforms. Concerns about stress induced at the tantalum (Ta) liner-to-BCB interface resulting in partial delamination are discussed. While across-wafer uniformity has not been demonstrated, the viability of this WLP-compatible 3D platform has been shown.

CMP Compatibility of Partially Cured Benzocyclobutene (BCB) for a Via-First 3D IC Process

2005 ◽  
Vol 867 ◽  
Author(s):  
J. J. McMahon ◽  
F. Niklaus ◽  
R. J. Kumar ◽  
J. Yu ◽  
J.Q. Lu ◽  
...  
Keyword(s):  
High Performance ◽  
Removal Rate ◽  
Three Dimensional ◽  
Surface Damage ◽  
Wafer Level ◽  
Razor Blade ◽  
3D Ic ◽  
3D Technology ◽  
Process Step ◽  
Wide Range

AbstractWafer-level three dimensional (3D) IC technology offers the promise of decreasing RC delays by reducing long interconnect lines in high performance ICs. This paper focuses on a viafirst 3D IC platform, which utilizes a back-end-of-line (BEOL) compatible damascene-patterned layer of copper and Benzocyclobutene (BCB). This damascene-patterned copper/BCB serves as a redistribution layer between two fully fabricated wafer sets of ICs and offers the potential of high bonding strength and low contact resistance for inter-wafer interconnects between the wafer pair. The process would thus combine the electrical advantages of 3D technology using Cu-to-Cu bonding with the mechanical advantages of 3D technology using BCB-to-BCB bonding.In this work, partially cured BCB has been evaluated for copper damascene patterning using commercially available CMP slurries as a key process step for a via-first 3D process flow. BCB is spin-cast on 200 mm wafers and cured at temperatures ranging from 190°C to 250°C, providing a wide range of crosslink percentage. These films are evaluated for CMP removal rate, surface damage (surface scratching and embedded abrasives), and planarity with commercially available copper CMP slurries. Under baseline process parameters, erosion, and roughness changes are presented for single-level damascene test patterns. After wafers are bonded under controlled temperature and pressure, the bonding interface is inspected optically using glass-to-silicon bonded wafers, and the bond strength is evaluated by a razor blade test.

Active Device Performance after Fan-out Wafer-level Packaging Process

2018 ◽  
Author(s):  
Hong-Yu Li ◽  
Masaya Kawano ◽  
Simon Lim ◽  
Daniel Ismael Cereno ◽  
Vasarla Nagendra Sekhar
Keyword(s):  
Device Performance ◽  
Wafer Level ◽  
Active Device ◽  
Packaging Process ◽  
Wafer Level Packaging
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