Make experimental device to be a toy - the experimental teaching in Digital Logic Circuit course

Author(s):  
Shanshan Li ◽  
Ninghan Zheng ◽  
Yuchao Gao ◽  
Chengbin Quan ◽  
Weidong Liu
2013 ◽  
Vol 427-429 ◽  
pp. 1285-1288
Author(s):  
Kang Yi Wang

With the continuous development of large-scale integrated circuit technology, the importance of structural testing and testability design for digital logic circuit has become increasingly evident. In the testing domain, Bench is the most commonly used formats to describe a measured circuit. In order to test the measured circuit using computer, files with various formats must be converted to a netlist file which can be identified by computer. Lev format is a common netlist file. This paper mainly discusses how to convert the Bench file into Lev file, and it is proved by testing program correctness and robustness.


1969 ◽  
Vol 7 (1) ◽  
pp. 7 ◽  
Author(s):  
R. Srinivasan ◽  
K.R. Srinivasan
Keyword(s):  

2016 ◽  
Vol 858 ◽  
pp. 1103-1106 ◽  
Author(s):  
Hazem Elgabra ◽  
Amna Siddiqui ◽  
Shakti Singh

Silicon Carbide (SiC) is an attractive candidate for integrated circuits (ICs) in harsh environment applications due to its superior inherent electrical properties. Though current research is geared towards adapting existing silicon based digital logic technologies to 4H-SiC, the true merit of each technology in 4H-SiC has remained unclear. Creating logic technologies specifically for 4H-SiC, taking into account its electrical properties, is an area which remains unexplored. In this paper, we present a novel bipolar logic technology that is designed and optimized for 4H-SiC, and compare its performance with the prevalent bipolar technologies. The results show that the novel logic technology not only compares well with the conventional technologies in performance, but also features simpler design, smaller footprint, and a low transistor count.


2020 ◽  
Vol 17 (5) ◽  
pp. 2266-2272
Author(s):  
Nikita Kar Chowdhury ◽  
R. Dhanabal ◽  
V. N. Ramakrishnan

An analysis of low power 2–4 decoder and 4–16 decoders are made and comparing it with the proposed decoders. The decoder logic circuit have been made utilizing Dual Value Logic (DVL) and Transmission gate logic to actualize a fourteen transistors 2–4 decoder for limiting the transistor count. By utilizing 2–4 pre-decoders and post-decoders to execute 4–16 decoder. Blended digital logic is additionally utilized for this reason. In correlation we have execute a solitary 2–4 decoder with least transistor check and low power utilization which is utilized to structure a 4–16 decoder. CADENCE Virtuoso simulation at 90 nm technology is used and calculated the power and area. We thus made a tabular comparison of our results with the results from previous researches.


2019 ◽  
Vol 2019 ◽  
pp. 1-17 ◽  
Author(s):  
Oğuz Altun ◽  
Orhan Nooruldeen

Digitalization of handwritten documents has created a greater need for accurate online recognition of hand-drawn sketches. However, the online recognition of hand-drawn diagrams is an enduring challenge in human-computer interaction due to the complexity in extracting and recognizing the visual objects reliably from a continuous stroke stream. This paper focuses on the design and development of a new, efficient stroke-based online hand-drawn sketch recognition scheme named SKETRACK for hand-drawn arrow diagrams and digital logic circuit diagrams. The fundamental parts of this model are text separation, symbol segmentation, feature extraction, classification, and structural analysis. The proposed scheme utilizes the concepts of normalization and segmentation to isolate the text from the sketches. Then, the features are extracted to model different structural variations of the strokes that are categorized into the arrows/lines and the symbols for effective processing. The strokes are clustered using the spectral clustering algorithm based on p-distance and Euclidean distance to compute the similarity between the features and minimize the feature dimensionality by grouping similar features. Then, the symbol recognition is performed using modified support vector machine (MSVM) classifier in which a hybrid kernel function with a lion optimized tuning parameter of SVM is utilized. Structural analysis is performed with lion-based task optimization for recognizing the symbol candidates to form the final diagram representations. This proposed recognition model is suitable for simpler structures such as flowcharts, finite automata, and the logic circuit diagrams. Through the experiments, the performance of the proposed SKETRACK scheme is evaluated on three domains of databases and the results are compared with the state-of-the-art methods to validate its superior efficiency.


Author(s):  
Maitreyi Sharma ◽  
Sonal Nipane ◽  
Rachita ◽  
Krupa N. Jariwala ◽  
Rasika Khade
Keyword(s):  

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