Asymmetrical topology and entropy-based heterogeneous link for many-core massive data communication

2013 ◽  
Vol 16 (4) ◽  
pp. 679-691 ◽  
Author(s):  
Yu-hang Liu ◽  
Ming-fa Zhu ◽  
Li-min Xiao ◽  
Jue Wang
Keyword(s):  
Data Communication ◽  
Massive Data ◽  
Many Core

PARALLEL FFT ALGORITHMS ON NETWORK-ON-CHIPS

2009 ◽  
Vol 18 (02) ◽  
pp. 255-269 ◽  
Author(s):  
JUN HO BAHN ◽  
JUNG SOOK YANG ◽  
WEN-HSIANG HU ◽  
NADER BAGHERZADEH
Keyword(s):  
Data Communication ◽  
Digital Signal ◽  
Variable Number ◽  
Data Locality ◽  
Communication Traffic ◽  
On Chip ◽  
Fft Algorithms ◽  
Signal Processors ◽  
Parallel Fft ◽  
Parallel Fft Algorithm

This paper presents parallel FFT algorithms with different degree of computation and communication overheads for multiprocessors in a Network-on-Chip (NoC) environment. Of the three parallel FFT algorithms presented in this paper, we propose two parallel FFT algorithms for a 2D NoC that can contain a variable number of processing elements (PEs) and one is a reference parallel FFT algorithm for comparison. A parallel FFT algorithm we propose increases performance by assigning well-balanced computation tasks to PEs. The execution times are reduced because the algorithm uses data locality well to avoid unnecessary data exchanges among PEs and removes the overall idle periods by2 a balanced task scheduling. An enhanced version of this algorithm is suggested in which communication traffic is reduced. In this algorithm, returning transformed data to an original PE after one computation stage before sending them to a next PE for the following stage is removed. Instead, we propose a method that enables to keep regularity of the data communication and computations with twiddle factors. According to the simulation result from our cycle-accurate SystemC NoC model with a parametrizable 2-D mesh architecture, and the analysis of the algorithms in time and complexity, our proposed algorithms are shown to outperform the reference parallel FFT algorithm and FFT implementations on TI Digital Signal Processors (DSPs) that have similar specifications to our simulation environment.

Dual Monitoring Communication for Self-Aware Network-on-Chip

2012 ◽  
Vol 3 (3) ◽  
pp. 72-91
Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Cmos Technology ◽  
Network On Chip ◽  
Time Profile ◽  
Self Awareness ◽  
Monitoring Networks ◽  
Communication Architecture ◽  
Run Time ◽  
On Chip

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

scholarly journals Voltage controlled on-demand magnonic nanochannels

2020 ◽  
Vol 6 (40) ◽  
pp. eaba5457 ◽  
Author(s):  
Samiran Choudhury ◽  
Avinash Kumar Chaurasiya ◽  
Amrit Kumar Mondal ◽  
Bivas Rana ◽  
Katsuya Miura ◽  
...  
Keyword(s):  
Electric Field ◽  
Indium Tin Oxide ◽  
Data Communication ◽  
Perpendicular Magnetic Anisotropy ◽  
Plane Wave Method ◽  
On Demand ◽  
Oxide Electrodes ◽  
Light Scattering Spectroscopy ◽  
On Chip ◽  
The One

Development of energy-efficient on-demand magnonic nanochannels (MNCs) can revolutionize on-chip data communication and processing. We have developed a dynamic MNC array by periodically tailoring perpendicular magnetic anisotropy using the electric field. Brillouin light scattering spectroscopy is used to probe the spin wave (SW) dispersion of MNCs formed by applying a static electric field at the CoFeB/MgO interface through the one-dimensional stripe-like array of indium tin oxide electrodes placed on top of Ta/CoFeB/MgO/Al2O3 heterostructures. Magnonic bands, consisting of two SW frequency modes, appear with a bandgap under the application of moderate gate voltage, which can be switched off by withdrawing the voltage. The experimental results are reproduced by plane wave method–based numerical calculations, and simulated SW mode profiles show propagating SWs through nanochannels with different magnetic properties. The anticrossing between these two modes gives rise to the observed magnonic bandgap.

scholarly journals Low-Complexity Iterative Detection Algorithm for Massive Data Communication in IIoT

IEEE Access ◽  
2018 ◽  
Vol 6 ◽  
pp. 11166-11172 ◽  
Author(s):  
Yu Han ◽  
Zhenyong Wang ◽  
Dezhi Li ◽  
Qing Guo ◽  
Gongliang Liu
Keyword(s):  
Data Communication ◽  
Low Complexity ◽  
Detection Algorithm ◽  
Iterative Detection ◽  
Massive Data

scholarly journals Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-17 ◽  
Author(s):  
Emanuele Cannella ◽  
Onur Derin ◽  
Paolo Meloni ◽  
Giuseppe Tuveri ◽  
Todor Stefanov
Keyword(s):  
Real Life ◽  
Data Communication ◽  
Network On Chip ◽  
Process Migration ◽  
Model Of Computation ◽  
Process Networks ◽  
Time Migration ◽  
Migration Mechanism ◽  
Run Time ◽  
On Chip

System adaptivity is becoming an important feature of modern embedded multiprocessor systems. To achieve the goal of system adaptivity when executing Polyhedral Process Networks (PPNs) on a generic tiled Network-on-Chip (NoC) MPSoC platform, we propose an approach to enable the run-time migration of processes among the available platform resources. In our approach, process migration is allowed by a middleware layer which comprises two main components. The first component concerns the inter-tile data communication between processes. We develop and evaluate a number of different communication approaches which implement the semantics of the PPN model of computation on a generic NoC platform. The presented communication approaches do not depend on the mapping of processes and have been implemented on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented in two case studies with different communication characteristics. The second middleware component allows the actual run-time migration of PPN processes. To this end, we propose and evaluate a process migration mechanism which leverages the PPN model of computation to guarantee a predictable and efficient migration procedure. The efficiency and applicability of the proposed migration mechanism is shown in a real-life case study.

scholarly journals Reconfigurable High Performance Secured NoC Design Using Hierarchical Agent-based Monitoring System

2018 ◽  
Vol 8 (6) ◽  
pp. 4164
Author(s):  
Kendaganna Swamy S ◽  
Anand Jatti ◽  
Uma B. V
Keyword(s):  
Monitoring System ◽  
High Performance ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Data Communication ◽  
Multiprocessor System ◽  
Packet Routing ◽  
Distributed Agents ◽  
Agent Based ◽  
On Chip

With the rapid increase in demand for high performance computing, there is also a significant growth of data communication that leads to leverage the significance of network on chip. This paper proposes a reconfigurable fault tolerant on chip architecture with hierarchical agent based monitoring system for enhancing the performance of network based multiprocessor system on chip against faulty links and nodes. These distributed agents provide healthy status and congestion information of the network. This status information is used for further packet routing in the network with the help of XY routing algorithm. The functionality of Agent is enhanced not only to work as information provider but also to take decision for packet to either pass or stop to the processing element by setting the firewall in order to provide security. Proposed design provides a better performance and area optimization by avoiding deadlock and live lock as compared to existing approaches over network design.

scholarly journals Design techniques for passive wireless microsystems

2021 ◽  
Author(s):  
Xiongliang Lai
Keyword(s):  
Power Consumption ◽  
Transmission Rate ◽  
Data Communication ◽  
Modulation Scheme ◽  
Voltage Level ◽  
Passive Wireless Microsystems ◽  
Level Shifters ◽  
Wireless Microsystems ◽  
On Chip ◽  
Design Techniques

The unique advantage of harvesting power wirelessly has evolved passive wireless microsystems to a fast-growing high-impact technology. In this dissertation, several new design techniques are proposed for the increasingly stringent requirements of passive wireless microsystems. The absence of on-board batteries imposes ultralow power consumption of passive wireless microsystems. Recent research reveals that multi-voltage systems-on-a-chip dramatically reduce power consumption such that power-efficient on-chip voltage level shifters are critically needed. This dissertation proposes a novel set of voltage level shifters built upon diode-based clamper-rectifier configurations. The voltage level shifters are passively powered by incoming signals with no static current consumption and are able to shift the incoming signals bidirectionally to suit the different voltage domains. The shifting steps could be continuous and are not bounded by the discrete transistor thresholds and power rails. A second bottleneck of passive wireless microsystems is the wireless power-harvesting efficiency that limits the wireless communication distance and the on-chip circuitry complexity and functionality. This dissertation proposes a transformer-based impedance matching network that greatly improves the power transfer efficiency from the receiving antenna to the on-chip circuit loads. The transformer is also capable of automatically calibrating its input impedance to match to the antenna impedance by a novel low-power varactor current tuning technique. In passive wireless microsystems, data modulation scheme largely determines the power transmission efficiency and data communication speed. Exploiting the constant carrier envelop of FSK modulation, this dissertation proposes a dual-tank architecture for FSK receivers in passive wireless microsystems. The dual receiving tanks significantly improves the power conversion efficiency of on-chip AC-to-DC voltage multipliers by providing high-quality-factor resonating tank voltages at each of the alternating FSK carriers. High data transmission rate is also achieved by exploring the dual tanks in an all-digital and a voltage-level shifting FSK demodulators.

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