scholarly journals Design techniques for passive wireless microsystems

2021 ◽  
Author(s):  
Xiongliang Lai
Keyword(s):  
Power Consumption ◽  
Transmission Rate ◽  
Data Communication ◽  
Modulation Scheme ◽  
Voltage Level ◽  
Passive Wireless Microsystems ◽  
Level Shifters ◽  
Wireless Microsystems ◽  
On Chip ◽  
Design Techniques

The unique advantage of harvesting power wirelessly has evolved passive wireless microsystems to a fast-growing high-impact technology. In this dissertation, several new design techniques are proposed for the increasingly stringent requirements of passive wireless microsystems. The absence of on-board batteries imposes ultralow power consumption of passive wireless microsystems. Recent research reveals that multi-voltage systems-on-a-chip dramatically reduce power consumption such that power-efficient on-chip voltage level shifters are critically needed. This dissertation proposes a novel set of voltage level shifters built upon diode-based clamper-rectifier configurations. The voltage level shifters are passively powered by incoming signals with no static current consumption and are able to shift the incoming signals bidirectionally to suit the different voltage domains. The shifting steps could be continuous and are not bounded by the discrete transistor thresholds and power rails. A second bottleneck of passive wireless microsystems is the wireless power-harvesting efficiency that limits the wireless communication distance and the on-chip circuitry complexity and functionality. This dissertation proposes a transformer-based impedance matching network that greatly improves the power transfer efficiency from the receiving antenna to the on-chip circuit loads. The transformer is also capable of automatically calibrating its input impedance to match to the antenna impedance by a novel low-power varactor current tuning technique. In passive wireless microsystems, data modulation scheme largely determines the power transmission efficiency and data communication speed. Exploiting the constant carrier envelop of FSK modulation, this dissertation proposes a dual-tank architecture for FSK receivers in passive wireless microsystems. The dual receiving tanks significantly improves the power conversion efficiency of on-chip AC-to-DC voltage multipliers by providing high-quality-factor resonating tank voltages at each of the alternating FSK carriers. High data transmission rate is also achieved by exploring the dual tanks in an all-digital and a voltage-level shifting FSK demodulators.

scholarly journals Design techniques for passive wireless microsystems

2021 ◽  
Author(s):  
Xiongliang Lai
Keyword(s):  
Power Consumption ◽  
Transmission Rate ◽  
Data Communication ◽  
Modulation Scheme ◽  
Voltage Level ◽  
Passive Wireless Microsystems ◽  
Level Shifters ◽  
Wireless Microsystems ◽  
On Chip ◽  
Design Techniques

The unique advantage of harvesting power wirelessly has evolved passive wireless microsystems to a fast-growing high-impact technology. In this dissertation, several new design techniques are proposed for the increasingly stringent requirements of passive wireless microsystems. The absence of on-board batteries imposes ultralow power consumption of passive wireless microsystems. Recent research reveals that multi-voltage systems-on-a-chip dramatically reduce power consumption such that power-efficient on-chip voltage level shifters are critically needed. This dissertation proposes a novel set of voltage level shifters built upon diode-based clamper-rectifier configurations. The voltage level shifters are passively powered by incoming signals with no static current consumption and are able to shift the incoming signals bidirectionally to suit the different voltage domains. The shifting steps could be continuous and are not bounded by the discrete transistor thresholds and power rails. A second bottleneck of passive wireless microsystems is the wireless power-harvesting efficiency that limits the wireless communication distance and the on-chip circuitry complexity and functionality. This dissertation proposes a transformer-based impedance matching network that greatly improves the power transfer efficiency from the receiving antenna to the on-chip circuit loads. The transformer is also capable of automatically calibrating its input impedance to match to the antenna impedance by a novel low-power varactor current tuning technique. In passive wireless microsystems, data modulation scheme largely determines the power transmission efficiency and data communication speed. Exploiting the constant carrier envelop of FSK modulation, this dissertation proposes a dual-tank architecture for FSK receivers in passive wireless microsystems. The dual receiving tanks significantly improves the power conversion efficiency of on-chip AC-to-DC voltage multipliers by providing high-quality-factor resonating tank voltages at each of the alternating FSK carriers. High data transmission rate is also achieved by exploring the dual tanks in an all-digital and a voltage-level shifting FSK demodulators.

Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sujata S.B. ◽  
Anuradha M. Sandi
Keyword(s):  
Power Consumption ◽  
High Throughput ◽  
Data Communication ◽  
Injection Rate ◽  
Area Network ◽  
Verilog Hdl ◽  
Content Type ◽  
Chip Area ◽  
And Performance ◽  
On Chip

Purpose The small area network for data communication within routers is suffering from storage of packet, throughput, latency and power consumption. There are a lot of solutions to increase speed of commutation and optimization of power consumption; one among them is Network-on-chip (NoC). In the literature, there are several NoCs which can reconfigurable dynamically and can easily test and validate the results on FPGA. But still, NoCs have limitations which are regarding chip area, reconfigurable time and throughput. Design/methodology/approach To address these limitations, this research proposes the dynamically buffered and bufferless reconfigurable NoC (DB2R NoC) using X-Y algorithm for routing, Torus for switching and Flexible Direction Order (FDOR) for direction finding between source and destination nodes. Thus, the 3 × 3 and 4 × 4 DB2R NoCs are made free from deadlock, low power and latency and high throughput. To prove the applicability and performance analysis of DB2R NoC for 3 × 3 and 4 × 4 routers on FPGA, the 22 bits for buffered and 19 bit for bufferless designs have been successfully synthesized using Verilog HDL and implemented on Artix-7 FPGA development bond. The virtual input/output chips cope pro tool has been incorporated in the design to verify and debug the complete design on Artix-7 FPGA. Findings In the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR. Originality/value In the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.

scholarly journals A Hybrid Communication Scheme for Efficient and Low-Cost Deployment of Future Flying Ad-Hoc Network (FANET)

Drones ◽  
2019 ◽  
Vol 3 (1) ◽  
pp. 16 ◽  
Author(s):  
Muhammad Asghar Khan ◽  
Ijaz Mansoor Qureshi ◽  
Fahimullah Khanzada
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ad Hoc Network ◽  
Ad Hoc ◽  
Transmission Rate ◽  
Low Cost ◽  
Data Communication ◽  
Low Power Consumption ◽  
Time Data ◽  
Communication Scheme

In recent years, FANET-related research and development has doubled, due to the increased demands of unmanned aerial vehicles (UAVs) in both military and civilian operations. Equipped with more capabilities and unique characteristics, FANET is able to play a vital role in mission-critical applications. However, these distinctive features enforce a series of guidelines to be considered for its efficient deployment. Particularly, the use of FANET for on-time data communication services presents demanding challenges in terms of energy efficiency and quality of service (QoS). Proper use of communication architecture and wireless technology will assist to solve these challenges. Therefore, in this paper, we review different communication architectures, including the existing wireless technologies, in order to provide seamless wireless connectivity. Based on the discussions, we conclude that a multi-layer UAV ad-hoc network is the most suitable architecture for networking a group of heterogeneous UAVs, while Bluetooth 5 (802.15.1) is the most favored option because of its low-cost, low power consumption, and longer transmission range for FANET. However, 802.15.1 has the limitation of a lower data rate as compared to Wi-Fi (802.11). Therefore, we propose a hybrid wireless communication scheme so as to utilize the features of the high data transmission rate of 802.11 and the low-power consumption of 802.15.1. The proposed scheme significantly reduces communication cost and improves the network performance in terms of throughput and delay. Further, simulation results using the Optimized Network Engineering Tool (OPNET) further support the effectiveness of our proposed scheme.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

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