Abstract
Three-dimensional (3D) stacked integrated circuit (SIC) chips are one of the most promising technologies to achieve compact, high-performance, and energy-efficient architectures. However, they face a heat dissipation bottleneck due to the increased volumetric heat generation and reduced surface area. Previous work demonstrated that pin-fin enhanced microgap cooling, which provides fluidic cooling between layers could potentially address the heat dissipation challenge. In this paper, a compact multitier pin-fin single-phase liquid cooling model has been established for both steady-state and transient conditions. The model considers heat transfer between layers via pin-fins, as well as the convective heat removal in each tier. Spatially and temporally varying heat flux distribution, or power map, in each tier can be modeled. The cooling fluid can have different pumping power and directions for each tier. The model predictions are compared with detailed simulations using computational fluid dynamics/heat transfer (CFD/HT). The compact model is found to run 120–600 times faster than the CFD/HT model, while providing acceptable accuracy. Actual leakage power estimation is performed in this codesign model, which is an important contribution for codesign of 3D-SICs. For the simulated cases, temperatures could decrease 3% when leakage power estimation is adopted. This model could be used as electrical-thermal codesign tool to optimize thermal management and reduce leakage power.
System-Level Leakage Power Estimation Model for ASIC Designs