Low Power Two Stage Dynamic Comparator Circuit Design for Analog to Digital Converters

2018 ◽  
Author(s):  
S Vadivel ◽  
N S Nithya
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Analog To Digital Converters ◽  
Two Stage ◽  
Dynamic Comparator ◽  
Analog To Digital

A low-power low-offset dynamic comparator for analog to digital converters

2014 ◽  
Vol 45 (2) ◽  
pp. 256-262 ◽  
Author(s):  
Mohsen Hassanpourghadi ◽  
Milad Zamani ◽  
Mohammad Sharifkhani
Keyword(s):  
Low Power ◽  
Analog To Digital Converters ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Low Offset

scholarly journals A Low Power, High Speed 1.2 V Dynamic Comparator for Analog-to-Digital Converters

2020 ◽  
Vol 171 ◽  
pp. 1018-1026
Author(s):  
Sahil Jakhar ◽  
Vishal Singh Mandloi ◽  
Rupam Goswami ◽  
Kavindra Kandpal
Keyword(s):  
Low Power ◽  
High Speed ◽  
Analog To Digital Converters ◽  
Dynamic Comparator ◽  
Analog To Digital

scholarly journals 1.5mW,14.68V/µS-Low Power and High Speed Comparator Design for ADC Applications

2019 ◽  
Vol 8 (6S4) ◽  
pp. 1322-1326
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Analog To Digital Converters ◽  
Slew Rate ◽  
Two Stage ◽  
Analog To Digital ◽  
Low Offset ◽  
Medical Equipments

Advanced medical equipments embedded with the sensors, analog to digital converters (ADC) and other equipment. Gain amplifier and the comparator are key blocks in ADCs improvement. Comparator is the key element in achieving a low offset and high slew ratein the ADCs, in addition power and speed optimizationdesigns are preferred. To achieve high speed and low power a modified architecture of a comparator is introduced. A 5V two stage comparator is designed to meet the specifications as, offset value <8.4mV, power dissipation <1.5mW and slew rate>14.68V/µS. Cadence Virtuoso tools and SCL 0.18 µm technology parameters are used for design. Designed comparator shows improved slew rate and power consumption in comparison with the existing comparators

scholarly journals A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

2019 ◽  
Vol 1 (4) ◽  
Author(s):  
Jose‐Angel Diaz‐Madrid ◽  
Gines Domenech‐Asensi ◽  
Johann Hauer ◽  
Loreto Mateu
Keyword(s):  
Analog To Digital Converters ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Fully Differential

scholarly journals Low-Power and Low-Voltage Analog-to-Digital Converters for wearable EEG systems

10.5772/7875 ◽  
2009 ◽  
Author(s):  
J. M. Garciacutea Gonzaacutelez ◽  
E. Loacutepez-Morillo ◽  
F. Muntildeoz ◽  
H. ElGmili ◽  
R.G. Carvajal
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Analog To Digital Converters ◽  
Analog To Digital ◽  
Wearable Eeg

Compact Low-Power Analog-to-Digital Converters using Multi-State Spatial Wavefunction-Switched (SWS) FETs

2014 ◽  
Vol 23 (01n02) ◽  
pp. 1450005
Author(s):  
Murali Lingalugari ◽  
John Chandy ◽  
Faquir Jain ◽  
El-Sayed Hasaneen ◽  
Evan Heller
Keyword(s):  
Low Power ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Analog To Digital Converters ◽  
Data Conversion ◽  
Low Power Consumption ◽  
Quantum Mechanical ◽  
Multiple Quantum ◽  
Analog To Digital ◽  
Electron Wavefunction

In this paper, we propose a new architecture for analog-to-digital converters (ADCs) using multistate spatial wavefunction-switched field-effect transistors (SWSFETs). SWSFETs are multiple quantum coupled well devices, where the wells are stacked vertically and the electron wavefunction switches from one well to another with the change in gate voltage. Quantum mechanical simulations of 3-well InGaAs-AlInAs SWSFET structures are presented. The designs and simulations of 2-bit and 3-bit ADCs using SWSFETs result in low power consumption and reduced device count which improves the speed of the data conversion.

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