A low power low noise capacitively coupled chopper instrumentation amplifier in 130 nm CMOS for portable biopotential acquisiton systems

2013 ◽  
Author(s):  
A. N. Mohamed ◽  
H. N. Ahmed ◽  
M. Elkhatib ◽  
K. A. Shehata
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Instrumentation Amplifier ◽  
Capacitively Coupled

A 3.6 μW 60 nV/sqrtHz Capacitively-Coupled Instrumentation Amplifier for Biopotential Signal Recordings

2015 ◽  
Vol 24 (06) ◽  
pp. 1550089 ◽  
Author(s):  
Yin Zhou ◽  
Xiaobo Wu ◽  
Peng Sun ◽  
Menglian Zhao
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Frequency Noise ◽  
Noise Power ◽  
Current Feedback ◽  
Common Mode ◽  
Capacitively Coupled ◽  
Offset Voltage

This paper presents a low-power low-noise instrumentation amplifier (IA) intended for biopotential signal recordings. The IA is designed based on a capacitively-coupled topology, which achieves wide input common-mode range, high common-mode rejection ratio (CMRR) and low power consumption. To reduce low-frequency noise and output ripple at the same time, a combination of chopping and ping-pong auto-zeroing techniques, which is normally used in current-feedback IAs, is introduced for the capacitively-coupled topology in this paper. An intrinsic adverse effect of the proposed structure which causes additional ripple is analyzed. The DC electrode offset voltage is suppressed and the input impedance is boosted through feedback techniques. An improved switched-capacitor common mode feedback (SC CMFB) circuit is also presented. Test results show that the IA achieves an equivalent input-referred noise power spectrum density of 60 nV/sqrtHz and a noise efficiency factor (NEF) of 5.58. The bandwidth is 0.5 Hz to 10 kHz, covering most biopotential recording applications. The IA was implemented in 0.18-μm CMOS process. It occupies 0.27 mm2 core area and consumes 3.6 μA from a 1 V supply.

scholarly journals Low Noise, High Input Impedance Digital-Analog Hybrid Offset Suppression Amplifier for Wearable Dry Electrode ECG Monitoring

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 165 ◽  
Author(s):  
Weilin Xu ◽  
Taotao Wang ◽  
Xueming Wei ◽  
Hongwei Yue ◽  
Baolin Wei ◽  
...  
Keyword(s):  
Input Impedance ◽  
Electronic Device ◽  
Gain Control ◽  
Low Noise ◽  
Instrumentation Amplifier ◽  
High Input ◽  
High Input Impedance ◽  
Capacitively Coupled ◽  
Dry Electrode ◽  
Long Time

The portable real-time electrocardiogram (ECG) is a convenient and promising electronic device for cardiovascular diseases patients. However, unlike wet gel electrodes in traditional clinical applications, dry electrodes are competent for comfortable long-time wearing and can prevent skin ulceration. Its ultra-high source impedance and electrode offset (EOS) make traditional chopper amplifiers with low input impedance and limited EOS range difficult to apply to this area. To overcome these challenges, this paper proposes a novel chopper amplifier topology. This architecture includes a gain control loop, a ripple reduction loop, and a DC-servo loop (DSL). The proposed sampling input stage and digital-analog hybrid DSL are employed to boost input impedance and extend the EOS handing range. Designed with a 0.18 µm 1P6M 1.8 V CMOS salicide process, the proposed chopper capacitively coupled instrumentation amplifier achieves an ultra-high input impedance of 120 GΩ (<0.05 Hz) or 2.1 GΩ (0.6~250 Hz), an EOS handing range of ±325 mV and a low noise of 1.9 μVrms at 0.6~250 Hz. It occupies an area of 0.36 mm2 and only consumes a quiescent current of 11 μA.

A 790 nW Low-Noise Instrumentation Amplifier for Bio-Sensing Based On Gm-RSC Structure

2018 ◽  
Vol 27 (10) ◽  
pp. 1850157
Author(s):  
Tao Yin ◽  
Guocheng Huang ◽  
Xiaodong Xu ◽  
Yachao Zhang ◽  
Xinxia Cai ◽  
...  
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Instrumentation Amplifier ◽  
Rejection Ratio ◽  
Power Supply Rejection Ratio ◽  
Transconductance Amplifier ◽  
Low Power Dissipation ◽  
Amplifier Stage ◽  
Potential Recording ◽  
Operational Frequency

This paper presents a low-power low-noise instrumentation amplifier (IA) for bio-potential recording. The proposed IA is based on a novel Gm-RSC structure, whose gain is determined by the transconductance (Gm) and the equivalent resistance ([Formula: see text]) of the switched-capacitor (SC) load. The transconductance amplifier stage is based on the current-reuse telescope topology to achieve low noise at low-power dissipation. A resistor-controlled oscillator is designed to generate desirable operational frequency for SC load and to continuously tune the mid-band gain of the IA for different biomedical applications. Measurement results show that the input referred noise of the proposed IA is about 1.27[Formula: see text][Formula: see text]VRMS ([Formula: see text][Formula: see text]Hz) and the noise efficiency factor is 3.3. The range of tunable gain is from 28 to 40[Formula: see text]dB. The common mode rejection ratio and power supply rejection ratio at 50[Formula: see text]Hz are 72 and 78[Formula: see text]dB, respectively. The IA consumes only 660[Formula: see text]nA current at 1.2[Formula: see text]V supply and the active area of the IA is only 0.035[Formula: see text]mm2.

Low-power, low-noise instrumentation amplifier for physiological signals

1984 ◽  
Vol 22 (3) ◽  
pp. 272-274 ◽  
Author(s):  
G. H. Hamstra ◽  
A. Peper ◽  
C. A. Grimbergen
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Physiological Signals ◽  
Instrumentation Amplifier

scholarly journals A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing

Sensors ◽  
2020 ◽  
Vol 20 (7) ◽  
pp. 2059
Author(s):  
Xuan Thanh Pham ◽  
Ngoc Tan Nguyen ◽  
Van Truong Nguyen ◽  
Jong-Wook Lee
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Low Noise ◽  
Efficiency Factor ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Common Mode ◽  
Ultra Low Power ◽  
Power Efficient ◽  
Servo Loop

To realize an ultra-low-power and low-noise instrumentation amplifier (IA) for neural and biopotential signal sensing, we investigate two design techniques. The first technique uses a noise-efficient DC servo loop (DSL), which has been shown to be a high noise contributor. The proposed approach offers several advantages: (i) both the electrode offset and the input offset are rejected, (ii) a large capacitor is not needed in the DSL, (iii) by removing the charge dividing effect, the input-referred noise (IRN) is reduced, (iv) the noise from the DSL is further reduced by the gain of the first stage and by the transconductance ratio, and (v) the proposed DSL allows interfacing with a squeezed-inverter (SQI) stage. The proposed technique reduces the noise from the DSL to 12.5% of the overall noise. The second technique is to optimize noise performance using an SQI stage. Because the SQI stage is biased at a saturation limit of 2VDSAT, the bias current can be increased to reduce noise while maintaining low power consumption. The challenge of handling the mismatch in the SQI stage is addressed using a shared common-mode feedback (CMFB) loop, which achieves a common-mode rejection ratio (CMRR) of 105 dB. Using the proposed technique, a capacitively-coupled chopper instrumentation amplifier (CCIA) was fabricated using a 0.18-µm CMOS process. The measured result of the CCIA shows a relatively low noise density of 88 nV/rtHz and an integrated noise of 1.5 µVrms. These results correspond to a favorable noise efficiency factor (NEF) of 5.9 and a power efficiency factor (PEF) of 11.4.

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