A 3.6 μW 60 nV/sqrtHz Capacitively-Coupled Instrumentation Amplifier for Biopotential Signal Recordings

2015 ◽  
Vol 24 (06) ◽  
pp. 1550089 ◽  
Author(s):  
Yin Zhou ◽  
Xiaobo Wu ◽  
Peng Sun ◽  
Menglian Zhao
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Frequency Noise ◽  
Noise Power ◽  
Current Feedback ◽  
Common Mode ◽  
Capacitively Coupled ◽  
Offset Voltage

This paper presents a low-power low-noise instrumentation amplifier (IA) intended for biopotential signal recordings. The IA is designed based on a capacitively-coupled topology, which achieves wide input common-mode range, high common-mode rejection ratio (CMRR) and low power consumption. To reduce low-frequency noise and output ripple at the same time, a combination of chopping and ping-pong auto-zeroing techniques, which is normally used in current-feedback IAs, is introduced for the capacitively-coupled topology in this paper. An intrinsic adverse effect of the proposed structure which causes additional ripple is analyzed. The DC electrode offset voltage is suppressed and the input impedance is boosted through feedback techniques. An improved switched-capacitor common mode feedback (SC CMFB) circuit is also presented. Test results show that the IA achieves an equivalent input-referred noise power spectrum density of 60 nV/sqrtHz and a noise efficiency factor (NEF) of 5.58. The bandwidth is 0.5 Hz to 10 kHz, covering most biopotential recording applications. The IA was implemented in 0.18-μm CMOS process. It occupies 0.27 mm2 core area and consumes 3.6 μA from a 1 V supply.

scholarly journals A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing

Sensors ◽  
2020 ◽  
Vol 20 (7) ◽  
pp. 2059
Author(s):  
Xuan Thanh Pham ◽  
Ngoc Tan Nguyen ◽  
Van Truong Nguyen ◽  
Jong-Wook Lee
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Low Noise ◽  
Efficiency Factor ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Common Mode ◽  
Ultra Low Power ◽  
Power Efficient ◽  
Servo Loop

To realize an ultra-low-power and low-noise instrumentation amplifier (IA) for neural and biopotential signal sensing, we investigate two design techniques. The first technique uses a noise-efficient DC servo loop (DSL), which has been shown to be a high noise contributor. The proposed approach offers several advantages: (i) both the electrode offset and the input offset are rejected, (ii) a large capacitor is not needed in the DSL, (iii) by removing the charge dividing effect, the input-referred noise (IRN) is reduced, (iv) the noise from the DSL is further reduced by the gain of the first stage and by the transconductance ratio, and (v) the proposed DSL allows interfacing with a squeezed-inverter (SQI) stage. The proposed technique reduces the noise from the DSL to 12.5% of the overall noise. The second technique is to optimize noise performance using an SQI stage. Because the SQI stage is biased at a saturation limit of 2VDSAT, the bias current can be increased to reduce noise while maintaining low power consumption. The challenge of handling the mismatch in the SQI stage is addressed using a shared common-mode feedback (CMFB) loop, which achieves a common-mode rejection ratio (CMRR) of 105 dB. Using the proposed technique, a capacitively-coupled chopper instrumentation amplifier (CCIA) was fabricated using a 0.18-µm CMOS process. The measured result of the CCIA shows a relatively low noise density of 88 nV/rtHz and an integrated noise of 1.5 µVrms. These results correspond to a favorable noise efficiency factor (NEF) of 5.9 and a power efficiency factor (PEF) of 11.4.

scholarly journals A Low-Power, Low-Noise, Resistive-Bridge Microsensor Readout Circuit with Chopper-Stabilized Recycling Folded Cascode Instrumentation Amplifier

2021 ◽  
Vol 11 (17) ◽  
pp. 7982
Author(s):  
Gyuri Choi ◽  
Hyunwoo Heo ◽  
Donggeun You ◽  
Hyungseup Kim ◽  
Kyeongsik Nam ◽  
...  
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Readout Circuit ◽  
Output Stage ◽  
Current Feedback ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Folded Cascode

In this paper, a low-power and low-noise readout circuit for resistive-bridge microsensors is presented. The chopper-stabilized, recycling folded cascode current-feedback instrumentation amplifier (IA) is proposed to achieve the low-power, low-noise, and high-input impedance. The chopper-stabilized, recycling folded cascode topology (with a Monticelli-style, class-AB output stage) can enhance the overall noise characteristic, gain, and slew rate. The readout circuit consists of a chopper-stabilized, recycling folded cascode IA, low-pass filter (LPF), ADC driving buffer, and 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). The prototype readout circuit is implemented in a standard 0.18 µm CMOS process, with an active area of 12.5 mm2. The measured input-referred noise at 1 Hz is 86.6 nV/√Hz and the noise efficiency factor (NEF) is 4.94, respectively. The total current consumption is 2.23 μA, with a 1.8 V power supply.

A low noise CMOS instrumentation amplifier for TMR-effect-based magnetic sensors

2021 ◽  
pp. 2150178
Author(s):  
Wenbo Zhang ◽  
Weiping Chen ◽  
Liang Yin ◽  
Qiang Fu ◽  
Xinpeng Di ◽  
...  
Keyword(s):  
Low Noise ◽  
Magnetic Sensors ◽  
Instrumentation Amplifier ◽  
Noise Power ◽  
Current Feedback ◽  
Fully Differential ◽  
Noise Power Spectral Density ◽  
Power Spectral ◽  
Two Stages ◽  
Magnetic Resistance

This paper presents a low [Formula: see text] noise CMOS single-ended output instrumentation amplifier (IA) for tunneling magnetic resistance (TMR) sensors. For high DC gain and linearity, the amplifier employs three-stage current-feedback topology. For high CMRR and PSRR, the first two stages employ fully differential input. To maintain stability and lower the power dissipation, the amplifier employs trans-conductance with capacitance feedback compensation (TCFC) topology. The amplifier employs chopping technology and continuous-time AC-coupled ripple reduction loop to reduce [Formula: see text] noise and chopping ripple. The whole chip is fabricated using 0.35 [Formula: see text]m CMOS-BCD technology and the total area is 1 mm2. Test result shows an input-referred noise power spectral density (PSD) of 14 nV/[Formula: see text] is achieved with 1 Hz [Formula: see text] corner. The bandwidth is larger than 50 kHz [Formula: see text] with 20 pF load capacitor. The total current is 300 [Formula: see text]A at 5 V supply.

scholarly journals High-CMRR Low-Noise Fully Integrated Front-End for EEG Acquisition Systems

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1157 ◽  
Author(s):  
Robert Chebli ◽  
Mohamed Ali ◽  
Mohamad Sawan
Keyword(s):  
Low Noise ◽  
Common Mode ◽  
Fully Integrated ◽  
Dc Offset ◽  
Chopper Stabilization ◽  
Logarithmic Amplifier ◽  
Offset Voltage ◽  
High Cmrr ◽  
Programmable Gain ◽  
Stabilization Technique

We present in this paper a fully integrated low-noise high common-mode rejection ratio (CMRR) logarithmic programmable gain amplifier (LPGA) and chopped LPGA circuits for EEG acquisition systems. The proposed LPGA is based on a rail-to-rail true logarithmic amplifier (TLA) stage. The high CMRR achieved in this work is a result of cascading three amplification stages to construct the LPGA in addition to the lower common-mode gain of the proposed logarithmic amplification topology. In addition, the 1 / f noise and the inherent DC offset voltage of the input transistors are reduced using a chopper stabilization technique. The CMOS 180 nm standard technology is used to implement the circuits. Experimental results for the integrated LPGA show a CMRR of 140 dB, a differential gain of 37 dB, an input-referred noise of 0.754 μ Vrms, a 189 μ W power consumption from 1.8 V power supply and occupies an active area of 0.4 mm 2 .

scholarly journals A 219-µW ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar
Keyword(s):  
Low Power ◽  
Ieee 802.15.4 ◽  
Low Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Process Technology ◽  
Ultra Low Power ◽  
Power Mode ◽  
Noise Amplifier

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

scholarly journals A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6456
Author(s):  
Fernando Cardes ◽  
Nikhita Baladari ◽  
Jihyun Lee ◽  
Andreas Hierlemann
Keyword(s):  
Low Power ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Second Order ◽  
Frequency Noise ◽  
Voltage Controlled Oscillator ◽  
Noise Shaping ◽  
Delta Sigma Modulator ◽  
Delta Sigma

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.

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