scholarly journals A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1769 ◽  
Author(s):  
Choongkeun Lee ◽  
Taegun Yim ◽  
Hongil Yoon
Keyword(s):  
High Speed ◽  
Negative Charge ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Clock Generator ◽  
Area Overhead ◽  
Pumping Efficiency ◽  
Charge Pump Circuit ◽  
Low Supply Voltage

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

A novel low voltage and high speed CMOS charge pump circuit

2010 ◽  
Author(s):  
Fan Qiang ◽  
Fu Xiansong ◽  
Niu Pingjuan ◽  
Yang Guanghua ◽  
Gao Tiecheng
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Charge Pump ◽  
Charge Pump Circuit

A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP

2005 ◽  
Vol 14 (05) ◽  
pp. 997-1006 ◽  
Author(s):  
ROBERT C. CHANG ◽  
LUNG-CHIH KUO ◽  
HOU-MING CHEN
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Low Power Cmos ◽  
Charge Pump Circuit ◽  
Frequency Detector

A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can be generated with a single supply voltage of 1.5 V. The power dissipation of the circuit is 9.17 mW.

scholarly journals Review a Low Power CMOS Charge Pump using Power Gating Techniques to Reduce Leakage Power

2018 ◽  
Vol 7 (3.1) ◽  
pp. 27
Author(s):  
Vengadeswari N ◽  
Priscilla Whitin
Keyword(s):  
Supply Voltage ◽  
Charge Pump ◽  
Major Elements ◽  
Leakage Power ◽  
Power Gating ◽  
Charge Pumps ◽  
Pumping Efficiency ◽  
Low Power Cmos ◽  
Two Parameters ◽  
Charge Pump Circuit

In most case, charge pump circuit is designed based on capacitor, where voltage is increased at each stage depending on each stage voltage gain. Major elements are all charge pumps circuits one is Pumping capacitors and diode connected MOS.To increases pumping efficiency is very higher for each stage of charge pump circuits. Pumping efficiency are limiting by two parameters one is parasitic capacitance and threshold voltage. The power dissipated from the circuit can be increased by attain of leakage current .To resist this leakage in the circuits the supply voltage is major concern. To reduce the leakage with the help of power gating technique .Charge pump circuits are to be designed and verified by using tanner t-spice tools. 

scholarly journals A HIGH EFFICIENCY CHARGE PUMP FOR LOW VOLTAGE DEVICES

2014 ◽  
pp. 16-19
Author(s):  
AAMNA ANIL ◽  
RAVI KUMAR SHARMA
Keyword(s):  
High Efficiency ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Charge Pumps ◽  
Nonvolatile Memories ◽  
A Charge ◽  
Low Supply Voltage ◽  
Capacitor Charge ◽  
Lower Voltage

A charge pump is a kind of DC to DC converter that uses capacitors as energy storage elements to create a higher or lower voltage power source. Charge pumps make use of switching devices for controlling the connection of voltage to the capacitor. Charge pumps have been used in the nonvolatile memories, such as EEPROM and Flash memories, for the programming of the floating-gate devices. They can also be used in the low-supply-voltage switched-capacitor systems that require high voltage to drive the analog switched. This paper includes voltage analysis of different charge pumps. On the basis of voltage analysis a new charge pump is proposed.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals T/R RF Switch with 150 ns Switching Time and over 100 dBc IMD for Wideband Mobile Applications in Thick Oxide SOI Process

Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 507
Author(s):  
Behnam S. Rikan ◽  
David Kim ◽  
Kyung-Duk Choi ◽  
Arash Hejazi ◽  
Joon-Mo Yoo ◽  
...  
Keyword(s):  
Negative Charge ◽  
Switching Time ◽  
Supply Voltage ◽  
Charge Pump ◽  
Design Rule ◽  
Absolute Maximum ◽  
Optimum Number ◽  
Rf Switch ◽  
Voltage Range ◽  
Custom Made

This paper presents a fast-switching Transmit/Receive (T/R) Single-Pole-Double-Throw (SPDT) Radio Frequency (RF) switch. Thorough analyses have been conducted to choose the optimum number of stacks, transistor sizes, gate and body voltages, to satisfy the required specifications. This switch applies six stacks of series and shunt transistors as big as 3.9 mm/160 nm and 0.75 mm/160 nm, respectively. A negative charge pump and a voltage booster generate the negative and boosted control voltages to improve the harmonics and to keep Inter-Modulation Distortion (IMD) performance of the switch over 100 dBc. A Low Drop-Out (LDO) regulator limits the boosted voltage in Absolute Maximum Rating (AMR) conditions and improves the switch performance for Process, Voltage and Temperature (PVT) variations. To reduce the size, a dense custom-made capacitor consisting of different types of capacitors has been presented where they have been placed over each other in layout considering the Design Rule Checks (DRC) and applied in negative charge pump, voltage booster and LDO. This switch has been fabricated and tested in a 90 nm Silicon-on-Insulator (SOI) process. The second and third IMD for all specified blockers remain over 100 dBc and the switching time as fast as 150 ns has been achieved. The Insertion Loss (IL) and isolation at 2.7 GHz are −0.17 dB and −33 dB, respectively. This design consumes 145 uA from supply voltage range of 1.65 V to 1.95 V and occupies 440 × 472 µm2 of die area.

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