Electroplating nanotwinned copper for ultrafine pitch redistribution layer (RDL) of advanced packaging technology

Author(s):  
Yu-Bo Zhang ◽  
Li-Yin Gao ◽  
Xiao Li ◽  
Zhe Li ◽  
Xu-Liang Ma ◽  
...  
Author(s):  
Takashi Saito ◽  
Tokuyuki Kitajima ◽  
Makoto Kawaguchi ◽  
Shinya Tajima ◽  
Masashi Okamoto

2016 ◽  
Vol 858 ◽  
pp. 889-893
Author(s):  
Woong Je Sung ◽  
B. Jayant Baliga

This paper aims to establish an intuitive model to determine the chip size of 1200V SiC MOSFET for a particular current rating. In order to provide the direction of next generation SiC MOSFETs, the most vital device parameters were investigated, and their quantitative influences are given. Cost analysis, based on the proposed method, shows that it is feasible to achieve the price parity to Silicon IGBTs by concurrent efforts such as improvements on the device innovation, advanced packaging technology, and reduced processing cost by leveraging high volume commercial 150 mm Si Foundries in US.


Author(s):  
Shuai-Lin Liu ◽  
Ward Ye ◽  
Yu-Po Wang ◽  
Long-Yuan Wang ◽  
Fred Lin

Abstract In recent years, the IC industry continues to drive demand in the consumer market, and more global sales of smart-phones, smart-watches and tablets have continued to grow. In order to continuously enhance high performance computing, the consumer products pursued began to integrate HBM (High Bandwidth Memory) and AI (Artificial Intelligence) to strong and powerful mainstream market. With the shrinking use space pursued by consumer products, it is necessary to continuously develop lighter and thinner products, and under such product conditions, it seems that the risks and difficulties of advanced packaging technology will be expected. Due to the ministration application, the warpage issue is the most influential factor in the following development of packaging technology. In this paper, we would like to overcome the poor strip warpage, not only to choose the EMC material form CTE property, but to think about improving the warpage from the machine process. The residual stress generated by the molding process of thermosetting resins exerts serious influences upon the mechanical properties, so we use Laser area beam processing to reheat the EMC and use the vacuum suction to reshape the warpage deformation. In this case, we verify the laser radiation time and peak temperature control of different strip types (including molded, thermal taped and ball attached molded strip) and EMC wafer form. We succeed to improve the maximum strip warpage from 17 um to 1um; wafer form from 13um to 3.5um. This laser beam reshape technology is proven to solve the warpage significantly for high density assembly.


1996 ◽  
Author(s):  
M.G. Armendariz ◽  
G.R. Hadley ◽  
M.E. Warren

Author(s):  
Satoshi Yamamoto ◽  
Masanobu Saruta ◽  
Hideyuki Wada ◽  
Michikazu Tomita ◽  
Tatsuo Suemasu

An advanced packaging technology with through-hole interconnections, which enables miniaturization and high-density packaging of electronic devices including MEMS devices and optical devices, has been developed. In this work, through-hole interconnections were applied to an image sensor packaging. Through-holes, 80μm in diameter and 200μm in depth, were formed from backside of the device wafer by Deep Reactive Ion Etching (DRIE). After an insulation layer was formed inside the holes, conductive material such as copper (Cu) or Gold-Tin (Au-Sn) alloy solder was filled into the holes by electroplating method or Molten Metal Suction Method (MMSM). This technology enables wafer-level packaging of the image sensor device. Some electrical characteristics and reliability performances including electric resistance, breakdown voltage, high-temperature storage test, heat cycle test, temperature-humidity test were examined. In this paper, fabrication processes, structural and electrical characteristics and reliability of the package will be reported.


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