Wafer-Level Packaging Technology With Through-Hole Interconnections in Silicon Substrate

2005 ◽  
Author(s):  
Satoshi Yamamoto ◽  
Masanobu Saruta ◽  
Hideyuki Wada ◽  
Michikazu Tomita ◽  
Tatsuo Suemasu
Keyword(s):  
Image Sensor ◽  
Electrical Characteristics ◽  
Mems Devices ◽  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging ◽  
Advanced Packaging ◽  
Resistance Breakdown ◽  
Paper Fabrication ◽  
Through Hole

An advanced packaging technology with through-hole interconnections, which enables miniaturization and high-density packaging of electronic devices including MEMS devices and optical devices, has been developed. In this work, through-hole interconnections were applied to an image sensor packaging. Through-holes, 80μm in diameter and 200μm in depth, were formed from backside of the device wafer by Deep Reactive Ion Etching (DRIE). After an insulation layer was formed inside the holes, conductive material such as copper (Cu) or Gold-Tin (Au-Sn) alloy solder was filled into the holes by electroplating method or Molten Metal Suction Method (MMSM). This technology enables wafer-level packaging of the image sensor device. Some electrical characteristics and reliability performances including electric resistance, breakdown voltage, high-temperature storage test, heat cycle test, temperature-humidity test were examined. In this paper, fabrication processes, structural and electrical characteristics and reliability of the package will be reported.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

Suspended high Q integrated inductor by wafer level packaging technology

2013 ◽  
Vol 21 (1) ◽  
pp. 215-219 ◽  
Author(s):  
M. Han ◽  
S. F. Wang ◽  
G. W. Xu ◽  
Le Luo
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
High Q ◽  
Integrated Inductor ◽  
Wafer Level Packaging

High Quality Integrated Inductor in Fan-out Wafer-Level Packaging Technology for mm-Wave Applications

2021 ◽  
Author(s):  
Kavin Senthil Murugesan ◽  
Mykola Chernobryvko ◽  
Sherko Zinal ◽  
Marco Rossi ◽  
Ivan Ndip ◽  
...  
Keyword(s):  
Wafer Level ◽  
High Quality ◽  
Packaging Technology ◽  
Integrated Inductor ◽  
Wafer Level Packaging

Wafer Level Micropackaging of MEMS Devices Using Thin Film Anodic Bonding

2002 ◽  
Vol 729 ◽  
Author(s):  
Lauren E. S. Rohwer ◽  
Andrew D. Oliver ◽  
Melissa V. Collins
Keyword(s):  
Shear Strength ◽  
Test Sample ◽  
Anodic Bonding ◽  
Mems Devices ◽  
Wafer Level ◽  
Thermal Actuators ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Leak Testing ◽  
Before And After

AbstractA wafer level packaging technique that involves anodic bonding of Pyrex wafers to released surface micromachined wafers is demonstrated. Besides providing a hermetic seal, this technique allows full wafer release, provides protection during die separation, and offers the possibility of integration with optoelectronic devices. Anodic bonding was performed under applied voltages up to 1000 V, and temperatures ranging from 280 to 400°C under vacuum (10-4Torr). The quality of the bonded interfaces was evaluated using shear strength testing and leak testing. The shear strength of Pyrex-to-polysilicon and aluminum bonds was ∼10-15 MPa. The functionality of surface micromachined polysilicon devices was tested before and after anodic bonding. 100% of thermal actuators, 94% of torsional ratcheting actuators, and 70% of microengines functioned after bonding. The 70% yield was calculated from a test sample of 25 devices.

Improved compensation for a reduction stepper to meet the challenges for advanced packaging applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000814-000819 ◽  
Author(s):  
James E Webb ◽  
Steven Gardner ◽  
Elvino DaSilveira
Keyword(s):  
Leading Edge ◽  
Image Features ◽  
Wafer Level ◽  
Projection Lens ◽  
Wafer Level Packaging ◽  
Alignment System ◽  
Wide Range ◽  
Advanced Packaging ◽  
Volume Production ◽  
Mix And Match

Advanced packaging manufacturers require steppers that will provide solutions for the challenges encountered with new advances in wafer-level packaging technologies such as TSV, eWLB, silicon and glass interposers being utilized in leading edge mobile devices. Step and repeat photolithography systems capable of finer imaging with tighter overlay are being introduced to meet the challenging manufacturing requirements associated with the mix and match needed for volume production on larger wafers. A 2X reduction stepper with unique features incorporated that extend the range of compensation is necessary to achieve the tighter specifications needed for many advanced packaging applications printed on 300 to 450mm wafers. A high throughput projection optical system is used to expose circuit patterns from a reticle mask onto a substrate to image features with the optimal fidelity required for advanced packaging technologies. The camera incorporates 350–450nm light from a mercury arc lamp that is transmitted through the mask containing circuit patterns. The imaging field prints a large 52mm × 66mm area in a single exposure. These features enable a system to process wafers in fewer shots which result in higher throughput using lower power. Substrates are positioned with a precise X, Y, Θ stage by locating marks using an off-axis, bright field alignment system with fully trainable mark feature capability. The approach results in precisely placed features within a layer and from layer to layer without directly referencing the reticle. The integrated metrology and precision positioning subsystem technologies are combined with a low distortion projection lens and a wide range of adjustments, allowing the stepper to be integrated into a production line in a mix and match setup with other lithography systems. This equipment can be used to image critical layers on substrates while ensuring grid registration and alignment with other lithography systems that are also printing images in the same process line. Several important global and intra-field image placement relationships for devices requiring multiple layer patterning have been combined in the stepper matching correction software. Further adjustment to the tool can be made to improve overlay when incorporated with fab-wide yield management software for automated, real-time process control. The types of adjustments needed and techniques that can be applied to compensate for image placement errors over large areas are discussed.

Electrical Chip-Board Interaction (e-CBI) of Wafer Level Packaging Technology

2017 ◽  
Vol 2017 (1) ◽  
pp. 000325-000330 ◽  
Author(s):  
Wei Zhao ◽  
Mark Nakamoto ◽  
Karthikeyan Dhandapani ◽  
Brian Henderson ◽  
Ron Lindley ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Measured Data ◽  
Circuit Board ◽  
Wafer Level ◽  
Test Chip ◽  
Chip Design ◽  
Packaging Technology ◽  
Printed Circuit ◽  
Wafer Level Packaging ◽  
Simulation Results

Abstract Electrical Chip Board Interaction (e-CBI) has emerged as a new risk in chip design as silicon die can directly interact with printed circuit board (PCB) in substrate-less wafer level packaging technology. To assess this risk Qualcomm Technologies, Inc. has converted an existing test chip to wafer level packaging technology. Both the measured data and simulation results show that e-CBI risk is significant and must be carefully managed.

Development of a wafer level packaging technology for high voltage applications

2018 ◽  
Author(s):  
Marion Volpert ◽  
Abdenacer Aitmani ◽  
Adrien Gasse ◽  
Brigitte Soulier ◽  
Patrick Peray ◽  
...  
Keyword(s):  
High Voltage ◽  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging
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