State of the Art Low Power (42mW per flip-flop) 150GHz+ CML Static Divider Implemented in Scaled 0.2 m Emitter-width InP DHBTs

This chapter presents a comprehensive overview of the conventional fully static master slave flip-flops used in low power VLSI systems where power budget is critical. In addition, the chapter also presents alternative realization of fully static master-slave flip-flops utilizing a modified feedback strategy. The flip-flops designed on the basis of modified architecture have been explained in detail and compared with state-of-the-art master slave flip-flop designs available in the literature. Extensive capacitance calculations have been performed in terms of clock load and capacitance at internal nodes has also been estimated for all the flip-flop configurations. This is executed in order to compare their relative power and delay characteristics which are well supported by simulation results.

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A CMOS phase/frequency detector with a high-speed low-power D-type master-slave flip-flop

The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002. ◽

10.1109/mwscas.2002.1187055 ◽

2004 ◽

Cited By ~ 2

Author(s):

Yubtzuan Chen ◽

Chih Ho Tu ◽

Jein Wu

Keyword(s):

Low Power ◽

High Speed ◽

Flip Flop ◽

Phase Frequency Detector ◽

Frequency Detector

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Timing characterization and layout of a low power differential C2MOS flip flop in 0.35μm technology

2008 2nd International Conference on Signals, Circuits and Systems ◽

10.1109/icscs.2008.4746891 ◽

2008 ◽

Cited By ~ 1

Author(s):

A. Dendouga ◽

N. Bouguechal ◽

S. Barra ◽

O. Manck

Keyword(s):

Low Power ◽

Flip Flop ◽

Power Differential

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A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

Journal of Circuits System and Computers ◽

10.1142/s0218126602000239 ◽

2002 ◽

Vol 11 (01) ◽

pp. 51-55

Author(s):

ROBERT C. CHANG ◽

L.-C. HSU ◽

M.-C. SUN

Keyword(s):

Power Consumption ◽

Low Power ◽

Power Dissipation ◽

High Speed ◽

Operating Frequency ◽

Flip Flop ◽

Lower Power ◽

Simulation Results ◽

Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

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