State-of-the-Art Master Slave Flip-Flop Designs for Low Power VLSI Systems

2016 ◽  
pp. 166-198
Author(s):  
Kunwar Singh ◽  
Satish Chandra Tiwari ◽  
Maneesha Gupta
Keyword(s):  
Low Power ◽  
State Of The Art ◽  
Relative Power ◽  
Power Budget ◽  
Comprehensive Overview ◽  
Feedback Strategy ◽  
Flip Flop ◽  
Simulation Results

This chapter presents a comprehensive overview of the conventional fully static master slave flip-flops used in low power VLSI systems where power budget is critical. In addition, the chapter also presents alternative realization of fully static master-slave flip-flops utilizing a modified feedback strategy. The flip-flops designed on the basis of modified architecture have been explained in detail and compared with state-of-the-art master slave flip-flop designs available in the literature. Extensive capacitance calculations have been performed in terms of clock load and capacitance at internal nodes has also been estimated for all the flip-flop configurations. This is executed in order to compare their relative power and delay characteristics which are well supported by simulation results.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

scholarly journals Tag Localization with Asynchronous Inertial-Based Shifting and Trilateration

Sensors ◽  
2019 ◽  
Vol 19 (23) ◽  
pp. 5204
Author(s):  
Alma’aitah ◽  
Eslim ◽  
Hassanein
Keyword(s):  
Low Power ◽  
Indoor Localization ◽  
State Of The Art ◽  
Location Estimation ◽  
Object Localization ◽  
Personal Area Networks ◽  
Matlab Simulation ◽  
Tag Localization ◽  
Simulation Results ◽  
Localization Data

Personal Area Networks (PAN) are key topologies in pervasive Internet of Things (IoT) localization applications. In the numerous object localization techniques, centralization and synchronization between the elements are assumed. In this paper, we leverage crowdsourcing from multiple fixed and mobile elements to enhance object localization. A cooperative crowdsourcing scheme is proposed to localize mobile low power tags using distributed and mobile/fixed readers for GPS assisted environments (i.e., outdoor) and fixed readers for indoors. We propose Inertial-Based Shifting and Trilateration (IBST) technique to provide an accurate reckoning of the absolute location of mobile tags. The novelty in our technique is its capability to estimate tag locations even when the tag is not covered by three readers to perform trilateration. In addition, IBST provides scalability since no processing is required by the low power tags. IBST technique is validated through extensive simulations using MATLAB. Simulation results show that IBST consistently estimates location, while other indoor localization solutions fail to provide such estimates as the state-of-the-art techniques require localization data to be available simultaneously to provide location estimation.

scholarly journals Designing a Novel High Performance Four-to-Two Compressor Cell Based on CNTFET Technology for Low Voltages

2018 ◽  
Vol 8 (6) ◽  
pp. 4863
Author(s):  
Mehdi Bagherizadeh ◽  
Mona Moradi ◽  
Mostafa Torabi
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
Critical Path ◽  
Low Power Design ◽  
Software Simulation ◽  
Majority Function ◽  
Simulation Results

<p>Compressor cell is often placed in critical path of multiplier circuits to perform partial product summation. Therefore it plays a significant role in determining the entire performance of multiplier and digital system. Respecting to the necessity of low power design for portable electronic, designing a low power and high performance compressors seems to be a good solution to overcome of these problems for computations. In this paper a novel high performance four-to-two compressor cell is proposed using Carbon Nanotube Field Effect Transistors (CNTFETs) technology. The new cell is based on Majority Function, NOR, and NAND gates. The main advantage of proposed design in comparison with former cells is the ease of obtaining CARRY output by means of Majority function. Simulations have been done with 32nm technology node using Synopsys HSPICE software. Simulation results confirm the priority of the proposed cell compared to other state-of-the-art four-to-two compressor cells.</p>

New Design of Scan Flip-Flop to Increase Speed and Reduce Power Consumption

2015 ◽  
Vol 24 (10) ◽  
pp. 1550159 ◽  
Author(s):  
Ramin Razmdideh ◽  
Ali Mahani ◽  
Mohsen Saneei
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Switching Activity ◽  
Flip Flop ◽  
Reduce Power Consumption ◽  
Controlled Switching ◽  
Simulation Results

In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented, in which short circuit current is controlled. Switching activity is decreased to reduce the consumed power of the scan flip-flop. Also, the total number of transistors through the path from input to the output is reduced and so the delay of the proposed scan flip-flop is decreased. Simulation results show 12% and 29% reduction in power consumption and delay of the proposed scan flip-flop, respectively. The results are given by comparison of our work with other scan flip-flops at 50% data switching activity.

Design and Analysis of Low Power CNTFET TSPC D - Flip Flop Based Shift Registers

2012 ◽  
Vol 229-231 ◽  
pp. 1651-1655 ◽  
Author(s):  
T. Ravi ◽  
V. Kannan
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Power Saving ◽  
Operating Voltage ◽  
Stanford University ◽  
Efficient Design ◽  
Flip Flop ◽  
Comparison Results ◽  
Simulation Results ◽  
Power Analyses

This paper enumerates the efficient design and analysis of low power CNTFET True single phase clock logic D Flip flop based shift registers. The TSPC D flip flop and shift registers are designed using Stanford University CNTFET model and proposed 10nm CNTFET model with sleepy keeper low power technique. The CNTFET is emerging as a viable replacement to the MOSFET. The transient and power analyses are obtained with operating voltage of 1V and the operating frequency at 1GHz. The simulation results are obtained and the analysis are compared with circuits designed using 32nm MOSFET. The comparison results are indicated that the proposed 10nm CNTFET based design and the low power technique are more efficient in power saving as compared to MOSFET design.

scholarly journals A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 802
Author(s):  
Heng You ◽  
Jia Yuan ◽  
Weidi Tang ◽  
Zenghui Yu ◽  
Shushan Qiao
Keyword(s):  
Low Power ◽  
High Speed ◽  
Input Data ◽  
Low Voltage ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Low Voltage Operation ◽  
Amplifier Stage ◽  
Simulation Results ◽  
Power Delay Product

In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm2 (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.

The all-optical flip-flop: state-of-the-art and perspectives

2008 ◽  
Author(s):  
Giancarlo Prati ◽  
Luca Potì ◽  
Antonella Bogoni
Keyword(s):  
State Of The Art ◽  
Flip Flop ◽  
All Optical
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