Process-temperature-frequency adaptive voltage scaled SRAM system for power reduction

2011 ◽  
Author(s):  
JiaFeng Zhu ◽  
Na Bai ◽  
JianHui Wu
2019 ◽  
Vol 5 (12) ◽  
pp. 37-46
Author(s):  
K. Chalov ◽  
Yu. Lugovoy ◽  
Yu. Kosivtsov ◽  
E. Sulman

This paper presents a study of the process of thermal degradation of crosslinked polyethylene. The kinetics of polymer decomposition was studied by thermogravimetry. Crosslinked polyethylene showed high heat resistance to temperatures of 400 °C. The temperature range of 430–500 °C was determined for the loss of the bulk of the sample. According to thermogravimetric data, the decomposition process proceeds in a single stage and includes a large number of fracture, cyclization, dehydrogenation, and other reactions. The process of pyrolysis of a crosslinked polymer in a stationary-bed metal reactor was investigated. The influence of the process temperature on the yield of solid, liquid, and gaseous pyrolysis products was investigated. The optimum process temperature was 500 °C. At this temperature, the yield of liquid and gaseous products was 85.0 and 12.5% (mass.), Respectively. Samples of crosslinked polyester decomposed almost completely. The amount of carbon–containing residue was 3.5% by weight of the feedstock. With increasing temperature, the yield of liquid products decreased slightly and the yield of gaseous products increased, but their total yield did not increase. For gaseous products, a qualitative and quantitative composition was determined. The main components of the pyrolysis gas were hydrocarbons C1–C4. The calorific value of pyrolysis gas obtained at a temperature of 500 °C was 17 MJ/m3. Thus, the pyrolysis process can be used to process crosslinked polyethylene wastes to produce liquid hydrocarbons and combustible gases.


2018 ◽  
Vol 6 (2) ◽  
pp. 1
Author(s):  
SEKHAR REDDY M. CHANDRA ◽  
REDDY P. RAMANA ◽  
◽  

Author(s):  
Sumit Saha ◽  
Arpit Singh ◽  
Maryam Shojaei Baghini ◽  
Mayank Goel ◽  
V. Ramgopal Rao
Keyword(s):  

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1587
Author(s):  
Duo Sheng ◽  
Hsueh-Ru Lin ◽  
Li Tai

High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.


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