Calibration of SAR analog-to-digital converters for expanding the sampling rate range

In this work, we analyze in depth multiple characteristic data of a representative population of radenv-ADCs (analog-to-digital converters able to operate under radiation). Selected ADCs behave without latch-up below 50 MeV·cm2/mg and are able to bear doses of ionizing radiation above 50 krad(Si). An exhaustive search of ADCs with radiation characterization data has been carried out throughout the literature. The obtained collection is analyzed and compared against the state of the art of scientific ADCs, which reached years ago the electrical performance that radenv-ADCs provide nowadays. In fact, for a given Nyquist sampling rate, radenv-ADCs require significantly more power to achieve lower effective resolution. The extracted performance patterns and conclusions from our study aim to serve as reference for new developments towards more efficient implementations. As tools for this purpose, we have conceived FOMTID and FOMSET, two new figures of merit to compare radenv-ADCs that consider electrical and radiation performance.

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Efficient CPS Method for Improving the Sampling Resolution of Periodic Signals

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.1077.235 ◽

2014 ◽

Vol 1077 ◽

pp. 235-240

Author(s):

Yun Chi Yeh ◽

Liuh Chii Lin ◽

Yuan Dong Chen

Keyword(s):

Phase Shift ◽

Sampling Rate ◽

Analog To Digital Converters ◽

Experimental Result ◽

Periodic Signal ◽

Analog To Digital ◽

Conversion Time ◽

Periodic Signals

Based on existing analog to digital converters (ADC), this study proposes a simple and reliable controlled phase shift (CPS) method to improve the sampling resolution of a periodic signal. The proposed method uses phase shifted sampling sets of a sequence of sampled periods to increase sample resolution. When combining these sets, the period is virtually sampled with a higher number of samples. The lower sampling rate (per period) alleviates the requirements to be imposed on the conversion time of the ADC. Under the original conversion time of ADC, the proposed method can provide more sampled signals. Experimental result shows the proposed CPS method can improve the sampling resolution of periodic signals.

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Different Analog to Digital Converters Architectures

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.d1641.029420 ◽

2020 ◽

Vol 9 (4) ◽

pp. 1256-1263

Keyword(s):

Signal To Noise Ratio ◽

Sampling Rate ◽

Digital Signal ◽

Vital Role ◽

Analog To Digital Converters ◽

Signal To Noise ◽

Analog To Digital ◽

Differential Nonlinearity ◽

Gain Error ◽

The Comparative Study

A series of recent studies has indicated that a mixed signal device analog to digital converters used for the processing of information and play a vital role in wireless sensors, Digital signal processing, Biomedical devices, in communication, IOT and various other applications. Across this broad use they give the significance in designing. The paper represents the various parameters like speed, area occupied, power consumption, sampling Rate, precision, Signal to noise ratio, Signal to noise distortion ratio, resolution, linearity and conversion time with respect to its different types and broad application in the real world. It defines errors due to non – linearity of signals as Differential nonlinearity, Integral nonlinearity, gain error, quantization error, aliasing and offset error. It also gives the comparative study about ADCs.

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A BISECTION-BASED POWER REDUCTION DESIGN FOR CMOS FLASH ANALOG-TO-DIGITAL CONVERTERS

Journal of Circuits System and Computers ◽

10.1142/s0218126609005459 ◽

2009 ◽

Vol 18 (05) ◽

pp. 933-945

Author(s):

CHIA-CHUN TSAI ◽

KAI-WEI HONG ◽

TRONG-YEN LEE

Keyword(s):

Power Consumption ◽

Supply Voltage ◽

Clock Cycle ◽

Sampling Rate ◽

Reducing Power ◽

Power Reduction ◽

Analog To Digital Converters ◽

Bisection Method ◽

Flash Adc ◽

Analog To Digital

In this paper, we present a bisection-based power reduction design for CMOS flash analog-to-digital converters (ADCs). A comparator-based inverter is employed along with two switches of an NMOS and a PMOS, the bisection method can let only half of comparators in a flash ADC work in every clock cycle for reducing power consumption. A practical example of 6-bit flash ADC operates at 200 MHz sampling rate and 3.3 V supply voltage is demonstrated. The power consumption of proposed circuit is only 40.75 mW with HSPICE simulation. Compared with the traditional flash ADC, our bisection method can reduce up to 43.18% in terms of power dissipation.

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