Process-strained Si (PSS) CMOS technology featuring 3D strain engineering

Author(s):  
C.-H. Ge ◽  
C.-C. Lin ◽  
C.-H. Ko ◽  
C.-C. Huang ◽  
Y.-C. Huang ◽  
...  
2009 ◽  
Vol 518 (5) ◽  
pp. 1595-1598 ◽  
Author(s):  
Shu-Tong Chang ◽  
Wei-Ching Wang ◽  
Chang-Chun Lee ◽  
Jacky Huang

2003 ◽  
Author(s):  
K. Rim ◽  
B.H. Lee ◽  
A. Mocuta ◽  
K. Jenkins ◽  
S. Bedell ◽  
...  

2008 ◽  
Vol 23 (2) ◽  
pp. 106-108
Author(s):  
Conal E. Murray ◽  
S. M. Polvino ◽  
I. C. Noyan ◽  
B. Lai ◽  
Z. Cai

Synchrotron-based X-ray microbeam measurements were performed on silicon-on-insulator (SOI) features strained by adjacent shallow-trench isolation (STI). Strain engineering in microelectronic technology represents an important aspect of the enhancement in complementary metal-oxide semiconductor device performance. Because of the complexity of the composite geometry associated with microelectronic circuitry, characterization of the strained Si devices at a submicron resolution is necessary to verify the expected strain distributions. The interaction region of the SOI strain extended the SOI film thickness from the STI edge at least 25 times. Regions of 65-nm-thick SOI less than 3 μm wide exhibited an overlap in the strain fields because of the surrounding STI. Microbeam mapping of arrays containing submicron SOI features and embedded STI structures revealed the largest out-of-plane strains because of the close proximity of superimposed strain distributions induced by the STI.


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