Real-space strain mapping of SOI features using microbeam X-ray diffraction

2008 ◽  
Vol 23 (2) ◽  
pp. 106-108
Author(s):  
Conal E. Murray ◽  
S. M. Polvino ◽  
I. C. Noyan ◽  
B. Lai ◽  
Z. Cai
Keyword(s):  
Semiconductor Device ◽  
Complementary Metal Oxide Semiconductor ◽  
Strain Engineering ◽  
Real Space ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Strain Mapping ◽  
Strained Si ◽  
X Ray ◽  
Out Of Plane

Synchrotron-based X-ray microbeam measurements were performed on silicon-on-insulator (SOI) features strained by adjacent shallow-trench isolation (STI). Strain engineering in microelectronic technology represents an important aspect of the enhancement in complementary metal-oxide semiconductor device performance. Because of the complexity of the composite geometry associated with microelectronic circuitry, characterization of the strained Si devices at a submicron resolution is necessary to verify the expected strain distributions. The interaction region of the SOI strain extended the SOI film thickness from the STI edge at least 25 times. Regions of 65-nm-thick SOI less than 3 μm wide exhibited an overlap in the strain fields because of the surrounding STI. Microbeam mapping of arrays containing submicron SOI features and embedded STI structures revealed the largest out-of-plane strains because of the close proximity of superimposed strain distributions induced by the STI.

Structural Change during the Formation of Directly Bonded Silicon Substrates

2011 ◽  
Vol 470 ◽  
pp. 158-163
Author(s):  
Tetsuji Kato ◽  
Takaya Ueda ◽  
Yuji Ohara ◽  
Jun Kikkawa ◽  
Yoshiaki Nakamura ◽  
...  
Keyword(s):  
Structural Changes ◽  
Semiconductor Device ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Diffusion Annealing ◽  
Silicon Substrates ◽  
X Ray ◽  
Transmission Electron ◽  
Characteristic Domain ◽  
Device Technology

The use of Si(011)/Si(001) direct silicon bonding (DSB) substrates is a key element of future complementary metal-oxide-semiconductor device technology. In the conventional bonding process, it is necessary to remove interfacial SiO2 to achieve direct atomic bonding. In this study, using X-ray microdiffraction and transmission electron microscopy, we investigate the structural changes caused by oxide out-diffusion annealing (ODA). It is revealed that crystallinity of the bonded Si(011) layer is degraded after low temperature ODA and gradually recovered with an increase in the ODA temperature and annealing time, which is well correlated with the interfacial SiO2/Si morphology. Characteristic domain textures depending on the ODA temperature are also detected.

scholarly journals Complete Ring Artifacts Reduction Procedure for Lab-Based X-ray Nano CT Systems

Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 238
Author(s):  
Jakub Šalplachta ◽  
Tomáš Zikmund ◽  
Marek Zemek ◽  
Adam Břínek ◽  
Yoshihiro Takeda ◽  
...  
Keyword(s):  
High Efficiency ◽  
Image Inpainting ◽  
Simulated Data ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Detection Accuracy ◽  
Reduction Procedure ◽  
X Ray ◽  
Artifacts Reduction ◽  
Ct Data

In this article, we introduce a new ring artifacts reduction procedure that combines several ideas from existing methods into one complex and robust approach with a goal to overcome their individual weaknesses and limitations. The procedure differentiates two types of ring artifacts according to their cause and character in computed tomography (CT) data. Each type is then addressed separately in the sinogram domain. The novel iterative schemes based on relative total variations (RTV) were integrated to detect the artifacts. The correction process uses the image inpainting, and the intensity deviations smoothing method. The procedure was implemented in scope of lab-based X-ray nano CT with detection systems based on charge-coupled device (CCD) and scientific complementary metal–oxide–semiconductor (sCMOS) technologies. The procedure was then further tested and optimized on the simulated data and the real CT data of selected samples with different compositions. The performance of the procedure was quantitatively evaluated in terms of the artifacts’ detection accuracy, the comparison with existing methods, and the ability to preserve spatial resolution. The results show a high efficiency of ring removal and the preservation of the original sample’s structure.

Novel Source Heterojunction Structures with Relaxed-/Strained-Layers for Quasi-Ballistic CMOS Transistors

2011 ◽  
Vol 470 ◽  
pp. 72-78 ◽  
Author(s):  
Tomohisa Mizuno ◽  
Mitsuo Hasegawa ◽  
Toshiyuki Sameshima
Keyword(s):  
Ion Implantation ◽  
Complementary Metal Oxide Semiconductor ◽  
Energy Difference ◽  
Oxide Semiconductor ◽  
Recoil Energy ◽  
The Novel ◽  
Mos Transistors ◽  
Oxide Interface ◽  
Strained Si ◽  
Strained Layers

We have studied new abrupt-source-relaxed/strained semiconductor-heterojunction structures for quasi-ballistic complementary-metal-oxide-semiconductor (CMOS) devices, by locally controlling the strain of a single strained semiconductor. Appling O+ ion implantation recoil energy to the strained semiconductor/buried oxide interface, Raman analysis of the strained layers indicates that we have successfully relaxed both strained-Si-on-insulator (SSOI) substrates for n-MOS and SiGe-on-insulator (SGOI) substrates for p-MOS without poly crystallizing the semiconductor layers, by optimizing O+ ion implantation conditions. As a result, it is considered that the source conduction and valence band offsets EC and EV can be realized by the energy difference in the source Si/channel-strained Si and the source-relaxed SiGe/channel-strained SiGe layers, respectively. The device simulator, considering the tunneling effects at the source heterojunction, shows that the transconductance of sub-10 nm source heterojunction MOS transistors (SHOT) continues to increase with increasing EC. Therefore, SHOT structures with the novel source heterojunction are very promising for future quasi-ballistic CMOS devices.

Innovative Curriculum on Electronic Materials Processing and Engingeering

2001 ◽  
Vol 684 ◽  
Author(s):  
Jane P. Chang
Keyword(s):  
Semiconductor Manufacturing ◽  
Chemical Engineering ◽  
Materials Science ◽  
Semiconductor Device ◽  
Electronic Materials ◽  
Dynamic Environment ◽  
Complementary Metal Oxide Semiconductor ◽  
Device Fabrication ◽  
Oxide Semiconductor ◽  
Solid State Physics

Recognizing that the traditional engineering education training is often inadequate in preparing the students for the challanges presented by this industry's dynamic environment and insufficient to meet the empoyer's criteria in hiring new engineers, a new curriculum on Semiconductor Manufacturing is instituted in the Chemical Engineering Department at UCLA to train the students in various scientific and technologica areas that are pertinenet to the microelectronics industries. This paper describes this new mutidisciplinary curriculum that provides knowledge and skills in semiconductor manufacturing through a series ofcourses that emphasize on the application of fundamenta engineeering disciplines in solid-state physics, materials science of semiconductors, and chemical processing. The curriculum comprises three major components:(1)a comprehensive course curriculum in semiconductor manufacturing; (2) a laboratory for hands-on training in semiconductor device fabrication; (3) design of experiments. The capstone laboratory course is designed to strengthen students’ training in “unit operatins” used in semicounductor manufacturing and allow them to practice engineering principles using the state-of-the-art experimental setup. It comprises the most comprehensive training(seven photolithographic steps and numero0us chemical processes)in fabricating and testing complementary metal-oxide-semiconductor (CMOS) devices. This curriculum is recentyaccredited by the Accreditation Board for Engineering and Technology(ABET).

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface

MRS Bulletin ◽  
1996 ◽  
Vol 21 (4) ◽  
pp. 38-44 ◽  
Author(s):  
F.K. LeGoues
Keyword(s):  
Metal Oxide ◽  
High Speed ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Strained Si

Recently much interest has been devoted to Si-based heteroepitaxy, and in particular, to the SiGe/Si system. This is mostly for economical reasons: Si-based technology is much more advanced, is widely available, and is cheaper than GaAs-based technology. SiGe opens the door to the exciting (and lucrative) area of Si-based high-performance devices, although optical applications are still limited to GaAs-based technology. Strained SiGe layers form the base of heterojunction bipolar transistors (HBTs), which are currently used in commercial high-speed analogue applications. They promise to be low-cost compared to their GaAs counterparts and give comparable performance in the 2-20-GHz regime. More recently we have started to investigate the use of relaxed SiGe layers, which opens the door to a wider range of application and to the use of SiGe in complementary metal oxide semiconductor (CMOS) devices, which comprise strained Si and SiGe layers. Some recent successes include record-breaking low-temperature electron mobility in modulation-doped layers where the mobility was found to be up to 50 times better than standard Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Even more recently, SiGe-basedp-type MOSFETS were built with oscillation frequency of up to 50 GHz, which is a new record, in anyp-type material for the same design rule.

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