Reliability of barrier engineered charge trapping devices for sub-30nm NAND flash

2009 IEEE International Electron Devices Meeting (IEDM) ◽

10.1109/iedm.2009.5424231 ◽

2009 ◽

Author(s):

Rich Liu ◽

Hang-Ting Lue ◽

K.C. Chen ◽

Chih-Yuan Lu

Keyword(s):

Charge Trapping ◽

Trapping Devices

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Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

2019 Electron Devices Technology and Manufacturing Conference (EDTM) ◽

10.1109/edtm.2019.8731328 ◽

2019 ◽

Author(s):

Joo Yun Seo ◽

Yoon Kim ◽

Sang-Ho Lee ◽

Daewoong Kwon ◽

Hee-Do Na ◽

...

Keyword(s):

Flash Memory ◽

Charge Trapping ◽

Nand Flash Memory ◽

High Scalability

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Theoretical Analysis of Planar Flat Floating Gate NAND Flash Device and Experimental Study of Floating-Gate (FG) / Charge-Trapping (CT) Fusion Device for Comprehensive Understanding of Charge Storage and Operation Principle

2016 IEEE 8th International Memory Workshop (IMW) ◽

10.1109/imw.2016.7495292 ◽

2016 ◽

Author(s):

Hang-Ting Lue ◽

Pei-Ying Du ◽

Roger Lo ◽

Chih-Yuan Lu

Keyword(s):

Experimental Study ◽

Theoretical Analysis ◽

Charge Trapping ◽

Floating Gate ◽

Charge Storage ◽

Comprehensive Understanding ◽

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The Effects of ONO thickness on Memory Characteristics in Nano-scale Charge Trapping Devices

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2007.378897 ◽

2007 ◽

Author(s):

Moon Kyung Kim ◽

SooDoo Chae ◽

Chung Woo Kim ◽

Jooyeon Kim ◽

S. Tiwari

Keyword(s):

Charge Trapping ◽

Memory Characteristics ◽

Trapping Devices

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Accurate program simulation of TANOS charge trapping devices

2008 9th Annual Non-Volatile Memory Technology Symposium (NVMTS) ◽

10.1109/nvmt.2008.4731201 ◽

2008 ◽

Author(s):

Thomas Melde ◽

M. Florian Beug ◽

Lars Bach ◽

Stephan Riedel ◽

Nigel Chan ◽

...

Keyword(s):

Charge Trapping ◽

Trapping Devices

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Statistical Investigation of Anomalous Fast Erase Dynamics in Charge Trapping NAND Flash

IEEE Electron Device Letters ◽

10.1109/led.2013.2247696 ◽

2013 ◽

Vol 34 (4) ◽

pp. 514-516 ◽

Author(s):

Cristian Zambelli ◽

Piero Olivo

Keyword(s):

Charge Trapping ◽

Statistical Investigation ◽

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Study of Counter-Pulse (CP) Programming Method to Improve the Vt Distribution for 3D Charge-Trapping NAND Flash Devices

2018 IEEE International Memory Workshop (IMW) ◽

10.1109/imw.2018.8388850 ◽

2018 ◽

Author(s):

Yung Chun Lee ◽

Wei-Chen Chen ◽

Hang-Ting Lue ◽

Chih-Chang Hsieh ◽

Kuo-Ping Chang ◽

...

Keyword(s):

Charge Trapping ◽

Programming Method ◽

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NON-VOLATILE HIGH SPEED & LOW POWER CHARGE TRAPPING DEVICES

Advanced Semiconductor Devices ◽

10.1142/9789812770332_0023 ◽

2007 ◽

Author(s):

Moon Kyung Kim ◽

Sandip Tiwari

Keyword(s):

Low Power ◽

Charge Trapping ◽

Trapping Devices

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Novel multi-bit non-uniform channel charge trapping memory device with virtual-source NAND flash array

Journal of Semiconductors ◽

10.1088/1674-4926/31/10/104009 ◽

2010 ◽

Vol 31 (10) ◽

pp. 104009

Author(s):

Gu Haiming ◽

Pan Liyang ◽

Zhu Peng ◽

Wu Dong ◽

Zhang Zhigang ◽

...

Keyword(s):

Charge Trapping ◽

Memory Device ◽

Virtual Source ◽

Uniform Channel ◽

Charge Trapping Memory

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Charge storage efficiency (CSE) effect in modeling the incremental step pulse programming (ISPP) in charge-trapping 3D NAND flash devices

2015 IEEE International Electron Devices Meeting (IEDM) ◽

10.1109/iedm.2015.7409635 ◽

2015 ◽

Author(s):

Wei-Chen Chen ◽

Hang-Ting Lue ◽

Yi-Hsuan Hsiao ◽

Tzu-Hsuan Hsu ◽

Xi-Wei Lin ◽

...

Keyword(s):

Charge Trapping ◽

Charge Storage ◽

Storage Efficiency ◽

Incremental Step

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Quantitative Model for Data Retention Loss at NROM Nitride Charge Trapping Devices after Program / Erase Cycling

2006 21st IEEE Non-Volatile Semiconductor Memory Workshop ◽

10.1109/.2006.1629503 ◽

2006 ◽

Author(s):

G. Tempel ◽

R. Hagenbeck ◽

M. Strassburg

Keyword(s):

Charge Trapping ◽

Quantitative Model ◽

Data Retention ◽

Retention Loss ◽

Trapping Devices

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