Parallel Computing of Graph-based Functions in ReRAM

Resistive Random Access Memory (ReRAM) is an emerging non-volatile memory technology. Besides its low power consumption and its high scalability, its inherent computation capabilities make ReRAM especially interesting for future computer architectures. Merging computations into the memory is a promising solution for overcoming the memory bottleneck. To perform computations in ReRAM, efficient synthesis strategies for Boolean functions have to be developed. In this article, we give a thorough presentation of how to employ parallel computing capabilities of ReRAM for the synthesis of functions given state-of-the-art graph-based representations AIGs or BDDs. Additionally, we introduce a new graph-based representation called m-And-Inverter Graph (m-AIGs), which allows us to fully exploit the computing capabilities of ReRAM. In the simulations, we show that our proposed approaches outperform state-of-the art synthesis strategies, and we show the superiority of m-AIGs over the standard AIG representation for ReRAM-based synthesis.

Integration technologies for chips with 2D materials

With compact footprint, low energy consumption, high scalability, and mass producibility, chip-scale integrated devices are an indispensable part of modern technological change and development. Recent advances in two-dimensional (2D) layered materials with their unique structures and distinctive properties have motivated their on-chip integration, yielding a variety of functional devices with superior performance and new features. To realize integrated devices incorporating 2D materials, it requires a diverse range of device fabrication techniques, which are of fundamental importance to achieve good performance and high reproducibility. This paper reviews the state-of-art fabrication techniques for the on-chip integration of 2D materials. First, an overview of the material properties and on-chip applications of 2D materials is provided. Second, different approaches used for integrating 2D materials on chips are comprehensively reviewed, which are categorized into material synthesis, on-chip transfer, film patterning, and property tuning / modification. Third, the methods for integrating 2D van der Waals heterostructures are also discussed and summarized. Finally, the current challenges and future perspectives are highlighted.

Efficient Solution for Large-Scale IoT Applications with Proactive Edge-Cloud Publish/Subscribe Brokers Clustering

Large-scale IoT applications with dozens of thousands of geo-distributed IoT devices creating enormous volumes of data pose a big challenge for designing communication systems that provide data delivery with low latency and high scalability. In this paper, we investigate a hierarchical Edge-Cloud publish/subscribe brokers model using an efficient two-tier routing scheme to alleviate these issues when transmitting event notifications in wide-scale IoT systems. In this model, IoT devices take advantage of proximate edge brokers strategically deployed in edge networks for data delivery services in order to reduce latency. To deliver data more efficiently, we propose a proactive mechanism that applies collaborative filtering techniques to efficiently cluster edge brokers with geographic proximity that publish and/or subscribe to similar topics. This allows brokers in the same cluster to exchange data directly with each other to further reduce data delivery latency. In addition, we devise a coordinative scheme to help brokers discover and bridge similar topic channels in the whole system, informing other brokers for data delivery in an efficient manner. Extensive simulation results prove that our model can adeptly support event notifications in terms of low latency, small amounts of relay traffic, and high scalability for large-scale, delay-sensitive IoT applications. Specifically, in comparison with other similar Edge-Cloud approaches, our proposal achieves the best in terms of relay traffic among brokers, about 7.77% on average. In addition, our model’s average delivery latency is approximately 66% of PubSubCoord-alike’s one.

Self-Rectified Graphite-Based Reprogrammable One-Time Programmable (RS-OTP) Memory for Embedded Applications

A graphite-based RRAM device with a self-rectifying characteristic named “non-linearity (NL)” is developed for a high-density crossbar array for in-memory computing with low power and high scalability. Meanwhile, the reprogrammable functions are presented in self-selected RRAM as a promising candidate for one-time programmable (OTP) in the emerging memory-embedded applications such as security, system-on-chip (SoC), and Internet of Things (IoT).

Fabrication techniques for the integration of 2D materials

<p><a>With compact footprint, low energy consumption, high scalability, and mass producibility, chip-scale integrated devices are an indispensable part of modern technological change and development. Recent advances in </a>two-dimensional (2D) layered materials with their unique structures and distinctive properties have motivated their on-chip integration, yielding a variety of functional devices with superior performance and new features. To realize integrated devices incorporating 2D materials, it requires a diverse range of device fabrication techniques, which are of fundamental importance to achieve good performance and high reproducibility. This paper reviews the state-of-art fabrication techniques for the on-chip integration of 2D materials. First, an overview of the material properties and on-chip applications of 2D materials is provided. Second, different approaches used for integrating 2D materials on chips are comprehensively reviewed, which are categorized into material synthesis, on-chip transfer, film patterning, and property tuning / modification. Third, the methods for integrating 2D van der Waals heterostructures are also discussed and summarized. Finally, the current challenges and future perspectives are highlighted.</p> <p><b> </b></p>

Fabrication techniques for the integration of 2D materials

<p><a>With compact footprint, low energy consumption, high scalability, and mass producibility, chip-scale integrated devices are an indispensable part of modern technological change and development. Recent advances in </a>two-dimensional (2D) layered materials with their unique structures and distinctive properties have motivated their on-chip integration, yielding a variety of functional devices with superior performance and new features. To realize integrated devices incorporating 2D materials, it requires a diverse range of device fabrication techniques, which are of fundamental importance to achieve good performance and high reproducibility. This paper reviews the state-of-art fabrication techniques for the on-chip integration of 2D materials. First, an overview of the material properties and on-chip applications of 2D materials is provided. Second, different approaches used for integrating 2D materials on chips are comprehensively reviewed, which are categorized into material synthesis, on-chip transfer, film patterning, and property tuning / modification. Third, the methods for integrating 2D van der Waals heterostructures are also discussed and summarized. Finally, the current challenges and future perspectives are highlighted.</p> <p><b> </b></p>

Fabrication Methods for Integrating 2D Materials

With compact footprint, low energy consumption, high scalability, and mass producibility, chip-scale integrated devices are an indispensable part of modern technological change and development. Recent advances in two-dimensional (2D) layered materials with their unique structures and distinctive properties have motivated their on-chip integration, yielding a variety of functional devices with superior performance and new features. To realize integrated devices incorporating 2D materials, it requires a diverse range of device fabrication techniques, which are of fundamental importance to achieve good performance and high reproducibility. This paper reviews the state-of-art fabrication techniques for the on-chip integration of 2D materials. First, an overview of the material properties and on-chip applications of 2D materials is provided. Second, different approaches used for integrating 2D materials on chips are comprehensively reviewed, which are categorized into material synthesis, on-chip transfer, film patterning, and property tuning / modification. Third, the methods for integrating 2D van der Waals heterostructures are also discussed and summarized. Finally, the current challenges and future perspectives are highlighted.

Performance of high scalability hybrid system of 10G-TDM-OCDMA-PON based on 2D-SWZCC code

A new architecture for increasing the number of simultaneous users in a hybrid system and providing a solution for the channel bottleneck problem has been designed and simulated. The 10G-TDM-OCDMA-PON system combines optical code division multiple access (OCDMA) and time-division multiplexed passive optical network (TDM-PON) techniques. The high bit rate TDM-PON system is based on a bit interleaving that uses noncontiguous order for data arranging manner, this system used to obtain ultra-high-speed data rate of 40 Gbps based on four TDM channels of 10 Gbps. The OCDMA system is based on two-dimensional single weight zero cross-correlation (2D-SWZCC) employing polarization and wavelength scheme with two orthogonal polarization angles (vertical and horizontal states). The proposed hybrid system increases the scalability by multiplexing M OCDMA codes in the same time slot of the TDM system that has N time slots. The results show that the proposed system with 2D-SWZCC has better performance with a high number of users and higher scalability than the system with 1D-SWZCC.

The pursuit of further miniaturization of screen printed micro paper-based analytical devices utilizing controlled penetration towards optimized channel patterning

One of the main objectives of microfluidic paper-based analytical devices is to present solutions particularly, for applications in low-resource settings. Therefore, screen-printing appears to be an attractive fabrication technique in the field, due to its overall simplicity, affordability, and high-scalability potential. Conversely, the minimum feature size attained using screen-printing is still rather low, especially compared to other fabrication methods, mainly attributed to the over-penetration of hydrophobic agents, underneath defined patterns on masks, into the fiber matrix of paper substrates. In this work, we propose the use of the over-penetration to our advantage, whereby an appropriate combination of hydrophobic agent temperature and substrate thickness, allows for the proper control of channel patterning, rendering considerably higher resolutions than prior arts. The implementation of Xuan paper and nail oil as novel substrate and hydrophobic agent, respectively, is proposed in this work. Under optimum conditions of temperature and substrate thickness, the resolution of the screen-printing method was pushed up to 97.83 ± 16.34 μm of channel width with acceptable repeatability. It was also found that a trade-off exists between achieving considerably high channel resolutions and maintaining high levels of repeatability of the process. Lastly, miniaturized microfluidic channels were successfully patterned on pH strips for colorimetric pH measurement, demonstrating its advantage on negligible sample-volume consumption in nano-liter range during chemical measurement and minimal interference on manipulation of precious samples, which for the first time, is realized on screen-printed microfluidic paper-based analytical devices.

A new limit on the resonant absorption of solar axions obtained via 169Tm-containing bolometer

A newly developed experimental technique based on 169Tm-containing cryogenic bolometer detector was employed in order to perform the search for solar axions. The inclusion of target material into the active detector volume allowed for significant increase in sensitivity to axion parameters. A short 6.6 days measurement campaign with 8.18 g detector crystal yielded the following limits on axion couplings: | g A γ ( g A N 0 + g A N 3 ) ≤ 1.44 × 10 − 14 GeV − 1 and | g A e ( g A N 0 + g A N 3 ) ≤ 2.81 × 10 − 16 . The achieved results demonstrate high scalability potential of presented experimental approach.