New method to study unlanded via architecture. Application to advanced interconnects: Al with low k and copper dual damascene

2002 ◽  
Author(s):  
P. Gayet ◽  
C. Lair ◽  
E. van den Vegt
Keyword(s):  
New Method ◽  
Dual Damascene ◽  
Low K

Electromigration failure distributions of dual damascene Cu /low – k interconnects

2006 ◽  
Vol 46 (9-11) ◽  
pp. 1581-1586 ◽  
Author(s):  
A.S. Oates ◽  
S.C. Lee
Keyword(s):  
Dual Damascene ◽  
Low K

Robust 130 mn-node Cu dual damascene technology with low-k barrier SiCN

2002 ◽  
Author(s):  
H. Aoki ◽  
K. Torii ◽  
T. Oshima ◽  
J. Noguchi ◽  
U. Tanaka ◽  
...  
Keyword(s):  
Dual Damascene ◽  
Low K

Novel Cu reflow seed process for Cu/low-k 64nm pitch dual damascene interconnects and beyond

2012 ◽  
Author(s):  
K. Motoyama ◽  
O. van der Straten ◽  
H. Tomizawa ◽  
J. Maniscalco ◽  
S.T. Chen
Keyword(s):  
Dual Damascene ◽  
Damascene Interconnects ◽  
Low K

Formation of highly reliable Cu/low-k interconnects by using CVD Co barrier in dual damascene structures

2011 ◽  
Author(s):  
Hye Kyung Jung ◽  
Hyun-Bae Lee ◽  
Matsuda Tsukasa ◽  
Eunji Jung ◽  
Jong-Ho Yun ◽  
...  
Keyword(s):  
Dual Damascene ◽  
Low K

Process-Oriented Stress Modeling and Stress Evolution During Cu/Low-K BEOL Processing

2004 ◽  
Vol 812 ◽  
Author(s):  
Charlie Jun Zhai ◽  
Paul R. Besser ◽  
Frank Feustel
Keyword(s):  
Stress State ◽  
Mechanical Stress ◽  
Plane Stress ◽  
Cmos Technology ◽  
Film Deposition ◽  
Stress Evolution ◽  
Process Step ◽  
Dual Damascene ◽  
Process Oriented ◽  
Low K

AbstractThe damascene fabrication method and the introduction of low-K dielectrics present a host of reliability challenges to Cu interconnects and fundamentally change the mechanical stress state of Cu lines. In order to capture the effect of individual process steps on the stress evolution in the BEoL (Back End of Line), a process-oriented finite element modeling (FEM) approach was developed. In this model, the complete stress history at any step of BEoL can be simulated as a dual damascene Cu structure is fabricated. The inputs to the model include the temperature profile during each process step and materials constants. The modeling results are verified in two ways: through wafer-curvature measurement during multiple film deposition processes and with X-Ray diffraction to measure the mechanical stress state of the Cu interconnect lines fabricated using 0.13um CMOS technology. The Cu line stress evolution is simulated during the process of multi-step processing for a dual damascene Cu/low-K structure. It is shown that the in-plane stress of Cu lines is nearly independent of subsequent processes, while the out-of-plane stress increases considerably with the subsequent process steps.

Mechanical Stress Influence on Electronic Transport in Low-$k$ SiOC Dielectric Dual Damascene Capacitor

2013 ◽  
Vol 34 (8) ◽  
pp. 1056-1058 ◽  
Author(s):  
Ya-Liang Yang ◽  
Tai-Fa Young ◽  
Ting-Chang Chang ◽  
Jia-Haw Hsu ◽  
Tsung-Ming Tsai ◽  
...  
Keyword(s):  
Mechanical Stress ◽  
Electronic Transport ◽  
Dual Damascene ◽  
Low K ◽  
Stress Influence

Lithography as a critical step for low-k dual damascene: from 248 nm to 193 nm

2002 ◽  
Author(s):  
K. Ronse ◽  
M. Maenhoudt ◽  
I. Pollentier ◽  
V. Wiaux ◽  
H. Struyf ◽  
...  
Keyword(s):  
Critical Step ◽  
Dual Damascene ◽  
193 Nm ◽  
Low K
Sign in / Sign up

Export Citation Format

Share Document