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Influence of a pocket doping in a Schottky tunneling FET
2013 IEEE International Meeting for Future of Electron Devices, Kansai
◽
10.1109/imfedk.2013.6602225
◽
2013
◽
Author(s):
Shilpi Guin
◽
Avik Chattopadhyay
◽
Anupam Karmakar
◽
Abhijit Mallik
Keyword(s):
Tunneling Fet
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References
Group IV/oxide semiconductor bi-layer tunneling FET
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
◽
10.1109/s3s46989.2019.9320690
◽
2019
◽
Author(s):
Shinichi Takagi
◽
Kimihiko Kato
◽
Mitsuru Takenaka
Keyword(s):
Group Iv
◽
Oxide Semiconductor
◽
Tunneling Fet
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Linearity Performance and Distortion Analysis of Carbon Nanotube Tunneling FET
Journal of Electronic Materials
◽
10.1007/s11664-020-08707-5
◽
2021
◽
Vol 50
(3)
◽
pp. 1496-1505
Author(s):
Sazzad Hussain
◽
Nafis Mustakim
◽
Jibesh Kanti Saha
Keyword(s):
Carbon Nanotube
◽
Tunneling Fet
◽
Distortion Analysis
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Impact-Ionization and Tunneling FET Characteristics of Dual-Functional Devices With Partially Covered Intrinsic Regions
IEEE Transactions on Nanotechnology
◽
10.1109/tnano.2015.2427453
◽
2015
◽
Vol 14
(4)
◽
pp. 633-637
◽
Cited By ~ 10
Author(s):
Minsuk Kim
◽
Youngin Jeon
◽
Yoonjoong Kim
◽
Sangsig Kim
Keyword(s):
Impact Ionization
◽
Dual Functional
◽
Tunneling Fet
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Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices
2015 International Conference on IC Design & Technology (ICICDT)
◽
10.1109/icicdt.2015.7165880
◽
2015
◽
Author(s):
Tse-Ching Wu
◽
Chien-Ju Chen
◽
Yin-Nien Chen
◽
Vita Pi-Ho Hu
◽
Pin Su
◽
...
Keyword(s):
Tunneling Fet
◽
Look Ahead
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Numerical Corrections to Estimate Depletion Region Width in Pseudo-two-dimensional Model of Double-Gate Tunneling FET
10.1109/niles53778.2021.9600561
◽
2021
◽
Author(s):
Muhammad Elgamal
◽
Ahmed Shaker
Keyword(s):
Depletion Region
◽
Double Gate
◽
Two Dimensional
◽
Dimensional Model
◽
Tunneling Fet
◽
Two Dimensional Model
◽
Gate Tunneling
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Novel Omega-Gate heterojunction tunneling FET with a new analytical model
Semiconductor Science and Technology
◽
10.1088/1361-6641/abf665
◽
2021
◽
Author(s):
Yihong Qing
◽
Te-Kuang Chiang
◽
Lin Wang
◽
Feibo Du
◽
Tiantian Xie
◽
...
Keyword(s):
Analytical Model
◽
Tunneling Fet
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Design guidelines to achieve minimum energy operation for ultra low voltage tunneling FET logic circuits
Japanese Journal of Applied Physics
◽
10.7567/jjap.54.04dc04
◽
2015
◽
Vol 54
(4S)
◽
pp. 04DC04
◽
Cited By ~ 12
Author(s):
Hiroshi Fuketa
◽
Kazuaki Yoshioka
◽
Koichi Fukuda
◽
Takahiro Mori
◽
Hiroyuki Ota
◽
...
Keyword(s):
Low Voltage
◽
Minimum Energy
◽
Logic Circuits
◽
Design Guidelines
◽
Tunneling Fet
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Promised Design of Energy-Efficient Negative-Capacitance Vertical Tunneling FET
ECS Journal of Solid State Science and Technology
◽
10.1149/2162-8777/ac10b4
◽
2021
◽
Author(s):
Narasimhulu Thoti
◽
Yiming Li
Keyword(s):
Energy Efficient
◽
Negative Capacitance
◽
Tunneling Fet
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Resonant tunneling through interface traps in nanowire tunneling FET
2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013)
◽
10.1109/nano.2013.6720817
◽
2013
◽
Cited By ~ 1
Author(s):
Hajime Nakamura
Keyword(s):
Resonant Tunneling
◽
Interface Traps
◽
Tunneling Fet
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(Invited) Tunneling FET Technologies Using III-V and Ge Materials
ECS Meeting Abstracts
◽
10.1149/ma2015-02/29/1084
◽
2015
◽
Keyword(s):
Tunneling Fet
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