A fully integrated W-band beamformer in 0.13-μm SiGe BiCMOS technology based on distributed true-time-delay architecture

2016 ◽  
Author(s):  
Zheng Wang
Keyword(s):  
Time Delay ◽  
Fully Integrated ◽  
True Time Delay ◽  
W Band ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
True Time

Analysis and Design of On-Chip RF Interconnect Line for Wideband True-Time Delay Line Application

2021 ◽  
pp. 2150146
Author(s):  
Yang Chen ◽  
Zhaoyang Qiu ◽  
Xiaofei Di ◽  
Xianqing Chen ◽  
Yu-Dong Zhang
Keyword(s):  
Time Delay ◽  
Delay Line ◽  
Delay Model ◽  
Analysis And Design ◽  
True Time Delay ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Relative Delay ◽  
True Time ◽  
On Chip

This paper presents the analytical resistance–capacitance–inductance–conductance (RLCG) model of the on-chip interconnect line (IL) based on its structure, and the proposed model can be used to design IL and analyze the delay characteristics. Using electromagnetic (EM) simulation, the relations between the inductance, quality factor and the width, length of IL are obtained, which verifies the proposed RLCG model of IL. The delay model of IL is derived and verified with respect to the effects of the [Formula: see text] and [Formula: see text] by simulation, which can provide the benefit for the true-time delay line (TTDL) design using IL. This work proposes the experiments on the delay characteristics of 3-bit TTDL with IL based on 0.13[Formula: see text][Formula: see text]m SiGe BiCMOS technology. The group delay and transient delay of the TTDL are measured, which exhibits a maximal relative delay of 35 ps with an average of 5 ps delay resolution over a frequency range of 14–34[Formula: see text]GHz. The results are consistent with the delay analysis based on the proposed IL model.

scholarly journals Fully-integrated 4-bit True Time Delay Module using Polymer Optical Switches and Waveguide Delay Lines

2006 ◽  
Author(s):  
Xiaolong Wang ◽  
Brie Howley ◽  
Maggie Y. Chen ◽  
Panoutsopoulos Basile ◽  
Ray T. Chen
Keyword(s):  
Time Delay ◽  
Optical Switches ◽  
Delay Lines ◽  
Fully Integrated ◽  
True Time Delay ◽  
True Time

RF MEMS Extended Tuning Range Varactor and Varactor Based True Time Delay Line Design

PIERS Online ◽  
2008 ◽  
Vol 4 (4) ◽  
pp. 433-436 ◽  
Author(s):  
Yaping Liang ◽  
Calvin W. Domier ◽  
Neville C. Luhmann, Jr.
Keyword(s):  
Time Delay ◽  
Delay Line ◽  
Tuning Range ◽  
Rf Mems ◽  
True Time Delay ◽  
True Time ◽  
Line Design

A multi-octave microwave 6-bit true time delay with low amplitude and delay variation in 65 nm CMOS

2021 ◽  
pp. 1-10
Author(s):  
Yakov Gutkin ◽  
Asher Madjar ◽  
Emanuel Cohen
Keyword(s):  
Time Delay ◽  
Insertion Loss ◽  
Impedance Matching ◽  
Least Significant Bit ◽  
Delay Cell ◽  
True Time Delay ◽  
Unit Cells ◽  
True Time ◽  
And Performance ◽  
Low Amplitude

Abstract In this paper, we describe the design, layout, and performance of a 6-bit TTD (true time delay) chip operating over the entire band of 2–18 GHz. The 1.15 mm2 chip is implemented using TSMC foundry 65 nm technology. The least significant bit is 1 ps. The design is based on the concept of all-pass network with some modifications intended to reduce the number of unit cells. Thus, the first three bits are implemented in a single delay cell. A peaking buffer amplifier between bit 4 and bit 5 is used for impedance matching and partial compensation of the insertion loss slope. The rms delay error of the TTD is <1 ps over most of the frequency band and insertion loss is between 2.5 and 6.3 dB for all 64 states.

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