Drain bias stress-induced degradation in amorphous silicon thin film transistors with negative gate bias

Author(s):  
Dapeng Zhou ◽  
Mingxiang Wang ◽  
Xiaowei Lu ◽  
Jie Zhou
2017 ◽  
Vol 32 (2) ◽  
pp. 91-96
Author(s):  
张猛 ZHANG Meng ◽  
夏之荷 XIA Zhi-he ◽  
周玮 ZHOU Wei ◽  
陈荣盛 CHEN Rong-sheng ◽  
王文 WONG Man ◽  
...  

1990 ◽  
Vol 192 ◽  
Author(s):  
Tetsu Ogawa ◽  
Sadayoshi Hotta ◽  
Horoyoshi Takezawa

ABSTRACTThrough the time and temperature dependence measurements on threshold voltage shifts (Δ VT) in amorphous silicon thin film transistors, it has been found that two separate instability mechanisms exist; within short stress time ranges Δ Vτ increases as log t and this behavior corresponds to charge trapping in SiN. On the other hand, in long stress time ranges Δ VT increases as t t/4 and can be explained by time-dependent creation of trap in a-Si.


2011 ◽  
Vol 98 (12) ◽  
pp. 122101 ◽  
Author(s):  
Chia-Sheng Lin ◽  
Ying-Chung Chen ◽  
Ting-Chang Chang ◽  
Fu-Yen Jian ◽  
Hung-Wei Li ◽  
...  

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