Increased terahertz emission from SI-GaAs deposited with sub-wavelength spacing metal line array

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

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Canalization of Sub-wavelength Images by Electromagnetic Crystals

PIERS Online ◽

10.2529/piers041207044900 ◽

2005 ◽

Vol 1 (1) ◽

pp. 37-41 ◽

Cited By ~ 3

Author(s):

Pavel A. Belov ◽

C. R. Simovski

Keyword(s):

Electromagnetic Crystals ◽

Sub Wavelength

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A Latent Issue of Via Resistance: Mechanism and Solution

10.31399/asm.cp.istfa2018p0121 ◽

2018 ◽

Author(s):

Wentao Qin ◽

Scott Donaldson ◽

Dan Rogers ◽

Lahcen Boukhanfra ◽

Julien Thiefain ◽

...

Keyword(s):

Thermal Stress ◽

Chemical Mechanical Planarization ◽

Resistance Mechanism ◽

Formation Enthalpy ◽

Metal Line ◽

Device Failure ◽

Valence Electrons ◽

Wafer Processing ◽

Field Failure ◽

And Tungsten

Abstract Many semiconductor products are manufactured with mature technologies involving the uses of aluminum (Al) lines and tungsten (W) vias. High resistances of the vias were sometimes observed only after electrical or thermal stress. A layer of Ti oxide was found on such a via. In the wafer processing, the post W chemical mechanical planarization (WCMP) cleaning left residual W oxide on the W plugs. Ti from the overlaying metal line spontaneously reduced the W oxide, through which Ti oxide formed. Compared with W oxide, the Ti oxide has a larger formation enthalpy, and the valence electrons of Ti are more tightly bound to the O ion cores. As a result, the Ti oxide is more resistive than the W oxide. Consequently, the die functioned well in the first test in the fab, but the via resistance increased significantly after a thermal stress, which led to device failure in the second test. The NH4OH concentration was therefore increased to more effectively remove residual W oxide, which solved the problem. The thermal stress had prevented the latent issue from becoming a more costly field failure.

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