Surface Electro-Static Discharge or mechanical damage: Solving the mystery of metal-to-metal shorts using an innovative failure analysis approach

2009 ◽  
Author(s):  
Lesly Endrinal ◽  
Edward Coyne
Keyword(s):  
Failure Analysis ◽  
Mechanical Damage ◽  
Analysis Approach ◽  
Static Discharge

An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages

2009 ◽  
Author(s):  
Michael Hertl ◽  
Diane Weidmann ◽  
Alex Ngai
Keyword(s):  
Thermal Stress ◽  
Failure Analysis ◽  
Deformation Measurement ◽  
Stress Conditions ◽  
Analysis Approach ◽  
New Approach ◽  
Reliability Improvement

Abstract A new approach to reliability improvement and failure analysis on ICs is introduced, involving a specifically developed tool for Topography and Deformation Measurement (TDM) under thermal stress conditions. Applications are presented including delamination risk or bad solderability assessment on BGAs during JEDEC type reflow cycles.

Analysis Approach on DMOS Transistor Vth Mismatch Due to Trapped Charges

2015 ◽  
Author(s):  
Hashim Ismail ◽  
Ang Chung Keow ◽  
Kenny Gan Chye Siong
Keyword(s):  
Failure Analysis ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Analysis Approach ◽  
Test Results ◽  
Root Cause ◽  
Switching Event ◽  
Output Transistor ◽  
Event Based ◽  
Trapped Charge

Abstract An output switching malfunction was reported on a bridge driver IC. The electrical verification testing revealed evidence of an earlier over current condition resulting from an abnormal voltage sense during a switching event. Based on these test results, we developed the hypothesis that a threshold voltage mismatch existed between the sense transistor and the output transistor. This paper describes the failure analysis approach we used to characterize the threshold voltage mismatch as well as our approach to determine the root cause, which was trapped charge on the gate oxide of the sense transistor.

scholarly journals Failure-Analysis Based Redesign of Furnace Conveyor System Components: A Case Study

Metals ◽  
2019 ◽  
Vol 9 (8) ◽  
pp. 816 ◽  
Author(s):  
Beatriz González-Ciordia ◽  
Borja Fernández ◽  
Garikoitz Artola ◽  
Maider Muro ◽  
Ángel Sanz ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Hot Stamping ◽  
Mechanical Damage ◽  
Lessons Learned ◽  
Press Hardening ◽  
Metallurgical Analysis ◽  
Standard Design ◽  
Failure Assessment ◽  
Improved Design

Any manufacturing equipment designed from scratch requires a detailed follow-up of the performance for the first units placed in service during the production ramp-up, so that lessons learned are immediately implemented in next deliveries and running equipment is accordingly updated. Component failure analysis is one of the most valuable sources of improvement among these lessons. In this context, a failure-assessment based design revision of the conveying system of a newly developed press hardening furnace is presented. The proposed method starts with a forensic metallurgical analysis of the failed components, followed by an investigation of the working conditions to ensure they match the forensic observations. The results of this approach evidenced an initially unforeseen thermo-mechanical damage produced by a combination of thermal distortions, material ageing, and mechanical fatigue. Once the cause–effect relationship for the failure is backed up by evidence, an improved design is proposed. As a conclusion, a new standard design for the furnace entrance set of rollers in hot stamping lines was established for roller hearth furnaces. The solution can be extended to similar applications, ensuring the same issues will not arise thanks to the lessons learned.

Environmental barrier coating (EBC) durability modeling using a progressive failure analysis approach

2012 ◽  
Author(s):  
Ali Abdul-Aziz ◽  
Galib Abumeri ◽  
William Troha ◽  
Ramakrishna T. Bhatt ◽  
Joseph E. Grady ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Progressive Failure ◽  
Analysis Approach ◽  
Environmental Barrier ◽  
Progressive Failure Analysis ◽  
Environmental Barrier Coating ◽  
Barrier Coating

Frontside and Backside Analysis of Surface ESD

2008 ◽  
Author(s):  
Dermot Daly ◽  
Linda Grogan ◽  
Fergal Keating
Keyword(s):  
Failure Analysis ◽  
Cross Sections ◽  
Assembly Process ◽  
Front Side ◽  
Final Test ◽  
Strong Case ◽  
Encapsulation Process ◽  
Metal Filament ◽  
Static Discharge

Abstract In an effort to understand the failing mechanism of power to ground (Vdd-GND) shorts found on FPGA devices by standard ATE methods at Final Test; the recently discovered ESDFOS (Electro Static Discharge from Outside to Surface)[1] mechanism was revealed as the perpetrator. This ESDFOS was first brought to the attention of the authors when it was seen in the May 2005 issue of the EDFA magazine [2].The physical signatures of ESDFOS such as cracked SiN passivation, Al metal filament spiking, SiO2 dielectric break down can often be related to other failing mechanisms and it can therefore be difficult to irrefutably associate those physical signature to ESDFOS and to make a strong case for action. In this paper standard front side FIB cross sections combined with a novel backside technique were used to establish that the failing devices underwent an ESDFOS event prior to the epoxy encapsulation process. Using the failure analysis results alterations were made to the assembly process which have reduced the occurrence of Vdd-GND shorts.

Identification of Wet Chemical Deprocessing Induced Artifacts—A Common Problem Affecting All MOS and CMOS Technologies

2016 ◽  
Author(s):  
Raymond G. Mendaros ◽  
Christian Renan B. Marquez ◽  
Bernardino D. Mazon
Keyword(s):  
Electric Fields ◽  
Integrated Circuit ◽  
Silicon Substrate ◽  
Mechanical Damage ◽  
Embedded Structures ◽  
Physical Attributes ◽  
Wet Chemical ◽  
Fabrication Defects ◽  
High Electric Fields ◽  
Static Discharge

Abstract Wet Chemical Deprocessing is one of the techniques in exposing embedded structures in an integrated circuit (IC). Layers of the die from the passivation to silicon substrate can be selectively etched using this technique. From series of evaluations conducted, it was discovered that there are silicon damage sites that are induced during wet chemical deprocessing. Their physical attributes are almost identical to the attributes of electro-static discharge (ESD) defects. It only differs in the locations where they occur. ESD defects are expected near the edges of the transistors’ gate channel where high electric fields are present while deprocessing artifacts are observed at the center of the gate channel. Deprocessing artifacts are represented by mechanically induced damage sites in the silicon substrate. These mechanical damage sites manifest in the form of silicon pits, voids, slits and fractures as a result of tensional or shearing stresses in the silicon substrate when the polysilicons separate from the silicon substrate. If deprocessing artifacts are not well understood by the analysts then these can be mistakenly reported as ESD or fabrication defects.

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