Frontside and Backside Analysis of Surface ESD

2008 ◽  
Author(s):  
Dermot Daly ◽  
Linda Grogan ◽  
Fergal Keating
Keyword(s):  
Failure Analysis ◽  
Cross Sections ◽  
Assembly Process ◽  
Front Side ◽  
Final Test ◽  
Strong Case ◽  
Encapsulation Process ◽  
Metal Filament ◽  
Static Discharge

Abstract In an effort to understand the failing mechanism of power to ground (Vdd-GND) shorts found on FPGA devices by standard ATE methods at Final Test; the recently discovered ESDFOS (Electro Static Discharge from Outside to Surface)[1] mechanism was revealed as the perpetrator. This ESDFOS was first brought to the attention of the authors when it was seen in the May 2005 issue of the EDFA magazine [2].The physical signatures of ESDFOS such as cracked SiN passivation, Al metal filament spiking, SiO2 dielectric break down can often be related to other failing mechanisms and it can therefore be difficult to irrefutably associate those physical signature to ESDFOS and to make a strong case for action. In this paper standard front side FIB cross sections combined with a novel backside technique were used to establish that the failing devices underwent an ESDFOS event prior to the epoxy encapsulation process. Using the failure analysis results alterations were made to the assembly process which have reduced the occurrence of Vdd-GND shorts.

A Method to Enhance the Front-Side Lapping Process for Localisation of Sub-Surface Defect for Advanced Packages

2018 ◽  
Author(s):  
Sze Yee Tan ◽  
Chiu Soon Wong ◽  
Chea Wee Lo ◽  
Cin Sheng Goh
Keyword(s):  
Failure Analysis ◽  
Surface Defect ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Assembly Process ◽  
Front Side ◽  
Root Cause ◽  
The Common ◽  
Thinning Process ◽  
Non Destructive

Abstract In the back-end assembly process, all of the packages will be tested prior to disposition to the customers in order to filter out any device with failure. For a reject unit with an unknown failure mechanism, it will be subjected to a comprehensive failure analysis (FA) to identify the root cause of the failure. Non-destructive verification, following by front-side decapsulation and internal physical inspection is the common way to visualise and identify the physical defect that usually causes the failure of a device during the back-end assembly process. For certain failures, visualization of the defect might not be straight forward after the decapsulation because the defect may be embedded or buried underneath a layer or wedge bond on the die. In this case, a more complicated FA analysis flow which comprises various precision techniques such as parallel lapping, hotspot localisation and focused-ion-beam (FIB) analyses will be needed to thin down the top layer/wedge bond for a precise localisation of the defect prior to precision analysis by FIB. However, the process to thin down the top layer/wedge bond with an exposed die of a partially decapsulated package is a tricky job as artefacts such as crack/scratches on die are likely to be introduced during the process of polishing. Also it is relatively difficult to control the thickness and levelling of the top layer/wedge bond during the thinning process. In this work, we developed a method that allows the analyst to re-cap the partially decapped package, and also to precisely measure and thin down the top layer to an accuracy of less than < 2um without the introduction of artefacts.

ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

1998 ◽  
Author(s):  
D.S. Patrick ◽  
L.C. Wagner ◽  
P.T. Nguyen
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Yield Enhancement ◽  
Production Test ◽  
Final Test ◽  
Critical Design ◽  
The Past ◽  
Product Engineering ◽  
Time Savings ◽  
Analysis Design

Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

Intermittent Failures in High Pin Count Packaging

2006 ◽  
Author(s):  
Ramesh Varma ◽  
Richard Brooks ◽  
Ronald Twist ◽  
James Arnold ◽  
Cleston Messick
Keyword(s):  
Failure Analysis ◽  
Shape Analysis ◽  
State Of The Art ◽  
Process Variation ◽  
High Reliability ◽  
Temperature Cycling ◽  
Assembly Process ◽  
System Failures ◽  
Industrial Grade ◽  
Corrective Actions

Abstract In a prequalification effort to evaluate the assembly process for the industrial grade high pin count devices for use in a high reliability application, one device exhibited characteristics that, without corrective actions and/or extensive screening, may lead to intermittent system failures and unacceptable reliability. Five methodologies confirmed this conclusion: (1) low post-decapsulation wire pull results; (2) bond shape analysis showed process variation; (3) Failure Analysis (FA) using state of the art equipment determined the root causes and verified the low wire pull results; (4) temperature cycling parts while monitoring, showed intermittent failures, and (5) parts tested from other vendors using the same techniques passed all limits.

Backside Mechanical Preparation Methodology for Effective Failure Analysis on Small and Non-Exposed Die Paddle Package

2018 ◽  
Author(s):  
Ong Pei Hoon ◽  
Ng Kiong Kay ◽  
Gwee Hoon Yen
Keyword(s):  
Failure Analysis ◽  
Chemical Etching ◽  
Chemical Resistance ◽  
Etching Time ◽  
Lead Frame ◽  
Front Side ◽  
Electrical Measurements ◽  
Mechanical Preparation ◽  
Die Surface ◽  
Copper Lead

Abstract Chemical etching is commonly used in exposing the die surface from die front-side and die backside because of its quick etching time, burr-free and stress-free. However, this technique is risky when performing copper lead frame etching during backside preparation on small and non-exposed die paddle package. The drawback of this technique is that the copper leads will be over etched by 65% Acid Nitric Fuming even though the device’s leads are protected by chemical resistance tape. Consequently, the device is not able to proceed to any other further electrical measurements. Therefore, we introduced mechanical preparation as an alternative solution to replace the existing procedure. With the new method, we are able to ensure the copper leads are intact for the electrical measurements to improve the effectiveness and accuracy of physical failure analysis.

Localization Techniques on a 0.15um CMOS Device: Charge Pump Failure Analysis

2002 ◽  
Author(s):  
Hui Pan ◽  
Thomas Gibson
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Charge Pump ◽  
Front Side ◽  
Pump Failure ◽  
Electrical Failure ◽  
Optical Proximity Correction ◽  
A Charge

Abstract In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.

DESIGN OF THE CROSS SECTION SHAPE OF AN ALUMINUM CRASH BOX FOR CRASHWORTHINESS ENHANCEMENT OF A CAR

2008 ◽  
Vol 22 (31n32) ◽  
pp. 5578-5583 ◽  
Author(s):  
S. B. KIM ◽  
H. HUH ◽  
G. H. LEE ◽  
J. S. YOO ◽  
M. Y. LEE
Keyword(s):  
Energy Absorption ◽  
Cross Section ◽  
Cross Sections ◽  
Rectangular Cross Section ◽  
Local Buckling ◽  
Absorption Capacity ◽  
Experimental Result ◽  
Displacement Curve ◽  
Front Side ◽  
Auto Body

This paper deals with the crashworthiness of an aluminum crash box for an auto-body with the various shapes of cross section such as a rectangle, a hexagon and an octagon. First, crash boxes with various cross sections were tested with numerical simulation to obtain the energy absorption capacity and the mean load. In case of the simple axial crush, the octagon shape shows higher mean load and energy absorption than the other two shapes. Secondly, the crash boxes were assembled to a simplified auto-body model for the overall crashworthiness. The model consists of a bumper, crash boxes, front side members and a sub-frame representing the behavior of a full car at the low speed impact. The analysis result shows that the rectangular cross section shows the best performance as a crash box which deforms prior to the front side member. The hexagonal and octagonal cross sections undergo torsion and local buckling as the width of cross section decreases while the rectangular cross section does not. The simulation result of the rectangular crash box was verified with the experimental result. The simulation result shows close tendency in the deformed shape and the load–displacement curve to the experimental result.

Direct Imaging of Device Characteristics In a Focused ion Beam System

1998 ◽  
Vol 4 (S2) ◽  
pp. 652-653 ◽  
Author(s):  
A. N. Campbell ◽  
J. M. Soden
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Material Removal ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Yield Enhancement ◽  
The Past ◽  
Design Changes ◽  
Design Debugging

A great deal can be learned about integrated circuits (ICs) and microelectronic structures simply by imaging them in a focused ion beam (FIB) system. FIB systems have evolved during the past decade from something of a curiosity to absolutely essential tools for microelectronics design verification and failure analysis. FIB system capabilities include localized material removal, localized deposition of conductors and insulators, and imaging. A major commercial driver for FIB systems is their usefulness in the design debugging cycle by (1) rewiring ICs quickly to test design changes and (2) making connection to deep conductors to facilitate electrical probing of complex ICs. FIB milling is also used for making precision cross sections and for TEM sample preparation of microelectronic structures for failure analysis and yield enhancement applications.

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