Threshold Voltage Instability of Commercial 1.2 kV SiC Power MOSFETs

We have observed a significant increase in the instability of SiC power MOSFET ID-VGS characteristics following bias stressing at elevated temperature, similar to the effect we previously observed following an ON-state current stress. Devices stressed by elevated temperature alone exhibited very little instability compared with devices stressed with both temperature and applied bias. These results, along with other results in the literature, suggest that this increase in threshold voltage instability at elevated temperature is due to the activation of additional near-interfacial oxide traps related to an O-vacancy defect known as an E′ center. It is important to develop improved processing methods to decrease the number of precursor oxide defect sites, since an increased negative shift can give rise to increased leakage current in the OFF-state and potential device failure if proper precautions are not met to provide an adequate margin for the threshold voltage.

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Critical Technical Issues in High Voltage SiC Power Devices

Materials Science Forum ◽

10.4028/www.scientific.net/msf.600-603.895 ◽

2008 ◽

Vol 600-603 ◽

pp. 895-900 ◽

Cited By ~ 14

Author(s):

Anant K. Agarwal ◽

Albert A. Burk ◽

Robert Callanan ◽

Craig Capell ◽

Mrinal K. Das ◽

...

Keyword(s):

Threshold Voltage ◽

Carrier Mobility ◽

Negative Charge ◽

State Of The Art ◽

Power Devices ◽

Power Mosfets ◽

Large Numbers ◽

Technical Issues ◽

The Difference ◽

Difficult Issue

In this paper, we review the state of the art of SiC switches and the technical issues which remain. Specifically, we will review the progress and remaining challenges associated with SiC power MOSFETs and BJTs. The most difficult issue when fabricating MOSFETs has been an excessive variation in threshold voltage from batch to batch. This difficulty arises due to the fact that the threshold voltage is determined by the difference between two large numbers, namely, a large fixed oxide charge and a large negative charge in the interface traps. There may also be some significant charge captured in the bulk traps in SiC and SiO2. The effect of recombination-induced stacking faults (SFs) on majority carrier mobility has been confirmed with 10 kV Merged PN Schottky (MPS) diodes and MOSFETs. The same SFs have been found to be responsible for degradation of BJTs.

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Mechanisms of Nitrogen Incorporation at 4H-SiC/SiO2 Interface during Nitric Oxide Passivation – A First Principles Study

Materials Science Forum ◽

10.4028/www.scientific.net/msf.858.465 ◽

2016 ◽

Vol 858 ◽

pp. 465-468 ◽

Cited By ~ 1

Author(s):

D.P. Ettisserry ◽

Neil Goldsman ◽

Akin Akturk ◽

Aivars J. Lelis

Keyword(s):

Nitric Oxide ◽

Silicon Dioxide ◽

First Principles ◽

Density Functional ◽

Oxygen Vacancies ◽

Functional Theory ◽

Power Mosfets ◽

Voltage Instability ◽

Nitrogen Incorporation ◽

Effective Mobility

In this work, we investigate the behavior of Nitrogen atoms at 4H-Silicon Carbide (4H-SiC)/Silicon dioxide (SiO2) interface during nitric oxide passivation using ab-initio Density Functional Theory. Our calculations suggest different possible energetically favorable and competing mechanisms by which nitrogen atoms could a) incorporate themselves into the oxide, just above the 4H-SiC substrate, and b) substitute for carbon atoms at the 4H-SiC surface. We attribute the former process to cause increased threshold voltage instability (hole traps), and the latter to result in improved effective mobility through channel counter-doping, apart from removing interface traps in 4H-SiC power MOSFETs. These results support recent electrical and XPS measurements. Additionally, Nitric Oxide passivation is shown to energetically favor re-oxidation of the 4H-SiC surface accompanied by the generation of oxygen vacancies under the conditions considered in this work.

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