An 1.1 V 0.1–1.6 GHz tunable-bandwidth elliptic filter with 6 dB linearity improvement by precise zero location control in 40 nm CMOS technology for 5G applications

A four-channel receiver front-end is designed and implemented for interference- and jamming-robust global navigation satellite system (GNSS) in a 0.18-μm CMOS technology. The front-end consists of four identical RF-to-IF signal paths including low-noise amplifiers (LNAs), mixers and IF amplifiers. In addition, it also includes a phase-locked loop (PLL), which synthesizes the local oscillator (LO) signal, and a serial peripheral interface (SPI) for parameter adjustment. To improve the interference and jamming robustness, a novel linearity improvement technology and LO duty cycle adjustment method are applied in LNA and mixer design, respectively. The receiver achieves a gain of 40 dB, an input-referred third-order intercept point (IIP3) of −8 dBm and a jammer-to-signal power ratio (JSR) of 72 dB under 1.8-V and 3.3-V supply, while occupying a 4 × 5 mm2 die area including the electrostatic discharge (ESD) I/O pads.

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A 5.2 GHz high gain high isolation double balance Gilbert cell mixer with linearity improvement in TSMC 180nm CMOS technology for WLAN application

2017 18th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA) ◽

10.1109/sta.2017.8314895 ◽

2017 ◽

Cited By ~ 1

Author(s):

Hanen Saoudi ◽

Mohamed Dhieb ◽

Hamadi Ghariani ◽

Mongi Lahiani

Keyword(s):

Cmos Technology ◽

High Gain ◽

High Isolation ◽

Linearity Improvement

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Linearity improvement of differential CMOS low noise amplifier

Indonesian Journal of Electrical Engineering and Computer Science ◽

10.11591/ijeecs.v14.i1.pp407-412 ◽

2019 ◽

Vol 14 (1) ◽

pp. 407

Author(s):

Maizan Muhamad ◽

Norhayati Soin ◽

Harikrishnan Ramiah

Keyword(s):

Integrated Circuit ◽

Wireless Lan ◽

Noise Figure ◽

Supply Voltage ◽

Cmos Technology ◽

Low Noise ◽

Low Noise Amplifier ◽

Common Source ◽

Linearity Improvement ◽

Noise Amplifier

This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S21 gain of 18.56 dB, noise figure (NF) of 1.85 dB, S11 of −27.63 dB, S22 of -34.33 dB, S12 of −37.09 dB and IIP3 of -7.79 dBm.

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