High Current [200 A], Low Resistance (0.87 mΩ-cm/sub 2/) Normally-off SiC VJFETs for Power Switching Applications

Author(s):  
E.J. Stewart ◽  
A.P. Walker ◽  
T.R. McNutt ◽  
S.D. Van Campen ◽  
H.C. Hearne ◽  
...  
2009 ◽  
Vol 19 (01) ◽  
pp. 129-135
Author(s):  
JUNXIA SHI ◽  
M. POPHRISTIC ◽  
L. F. EASTMAN

AlGaN / GaN heterojunction field effect transistors (HFETs) on sapphire substrates for power-switching applications have been fabricated. Design parameters such as source-gate spacing (Lsg), gate length (Lg), and gate width (Wg) have been varied to check their effects on the device performances. For a gate-drain spacing (Lgd) of 10µm, a specific on-resistance (ARon) of 1.35mΩ-cm2 and off-state breakdown voltage (BV) of 770V was achieved, which is close to the 4- H SiC theoretical limit.


2010 ◽  
Vol 645-648 ◽  
pp. 1227-1230 ◽  
Author(s):  
Shinichi Shikata ◽  
Hitoshi Umezawa ◽  
Hideaki Yamada ◽  
T. Tsubouchi ◽  
Yoshiaki Mokuno ◽  
...  

Diamond is a hopeful candidate for power switching device which can operate at high temperature as a “Cooling system free” device, yet at a high current. Recently we have developed a 3D diamond CVD growth method coupled with a sophisticated “direct wafer fabrication technique” to fabricate diamond wafer without slicing. Currently, half inch size single crystal diamond substrates are available for R&D of diamond device. Using this technique, we have increased the device fabrication size from 3x3mm2 to half inch wafer. In this paper, we present the results of measurements on the first device fabricated on a half inch size CVD substrate. We have carried out the first device characteristics mapping for diamond, and have observed the influence of substrate characteristics on the SBD characteristics.


2010 ◽  
Vol 645-648 ◽  
pp. 929-932 ◽  
Author(s):  
Victor Veliadis ◽  
Harold Hearne ◽  
Eric J. Stewart ◽  
R. Howell ◽  
Aivars J. Lelis ◽  
...  

A recessed implanted-gate short-channel 1290-V normally-OFF 4H-SiC vertical-channel JFET (VJFET), fabricated in seven photolithographic-levels, with a single masked ion-implantation and no epitaxial regrowth, is evaluated for efficient power conditioning. Under unipolar high-current-gain operation, which is required for efficient power switching, the 1200-V N-OFF (enhancement mode) VJFET exhibits prohibitively high on-state resistance. Comparison with 1200-V normally-ON VJFETs, fabricated on the same wafer, confirms experimentally that the strong gate-depletion-region overlap required for 1200-V normally-OFF blocking is the principal contributor to the prohibitively high specific on-state resistance observed under high current-gain VJFET operation. Recessed-implanted-gate VJFET channel-region optimization simulations (assuming a single commercial implantation and no epitaxial-regrowth) revealed that although aggressively increasing channel doping lowers resistance, the corresponding reduction in source mesa-width can prohibitively limit manufacturability.


2009 ◽  
Vol 615-617 ◽  
pp. 899-902 ◽  
Author(s):  
Peter A. Losee ◽  
Kevin Matocha ◽  
Steve Arthur ◽  
Eladio Delgado ◽  
Richard Beaupre ◽  
...  

The development of large area, up to 70m/1kV (0.45cm x 0.45cm) 4H-SiC vertical DMOSFETs is presented. DC and switching characteristics of high-current, 100Amp All-SiC power switching modules are demonstrated using 0.45cm x 0.225cm DMOSFET die and commercial Schottky diodes. The switching performance from room temperature up to T=200°C of the All-SiC modules is presented, with as much as ten times lower losses than co-fabricated Si-based modules using commercial IGBTs.


2018 ◽  
Vol 26 (5) ◽  
pp. 2426-2436
Author(s):  
Dragana PETROVIĆ ◽  
Miroslav LAZIĆ ◽  
Obrad ALEKSIĆ ◽  
Maria Vesna NIKOLIĆ ◽  
Vedran IBRAHIMOVIĆ ◽  
...  

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