Channel Surface Integrity with 2.4nm High-k Gate Dielectric under DPN Treatment at Different Annealing Temperatures

2021 ◽  
Author(s):  
Mu-Chun Wang ◽  
Cheng-Hsun-Tony Chang ◽  
Hao-Lun Hu ◽  
Zi-Wen Zhong ◽  
Guo-Xuan Qiu ◽  
...  
Keyword(s):  
Surface Integrity ◽  
Gate Dielectric ◽  
Annealing Temperatures ◽  
High K ◽  
Channel Surface ◽  
High K Gate Dielectric

Experimental observations of the thermal stability of high-k gate dielectric materials on silicon

2002 ◽  
Vol 303 (1) ◽  
pp. 54-63 ◽  
Author(s):  
P.S. Lysaght ◽  
P.J. Chen ◽  
R. Bergmann ◽  
T. Messina ◽  
R.W. Murto ◽  
...  
Keyword(s):  
Thermal Stability ◽  
Gate Dielectric ◽  
Dielectric Materials ◽  
High K ◽  
Thermal Stability Of ◽  
High K Gate Dielectric

scholarly journals High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

2012 ◽  
Vol 7 (1) ◽  
pp. 431 ◽  
Author(s):  
Szu-Hung Chen ◽  
Wen-Shiang Liao ◽  
Hsin-Chia Yang ◽  
Shea-Jue Wang ◽  
Yue-Gie Liaw ◽  
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Keyword(s):  
High Performance ◽  
Gate Dielectric ◽  
High K ◽  
High K Gate Dielectric
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