Compact models for double gate hetero gate dielectric nano scale Tunnel FET

2013 IEEE International Conference on Signal Processing, Computing and Control (ISPCC) ◽

10.1109/ispcc.2013.6663448 ◽

2013 ◽

Author(s):

B. Bhowmick ◽

S. Baishya ◽

C. Joishy

Keyword(s):

Gate Dielectric ◽

Double Gate ◽

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A charge-based capacitance model for double-gate hetero-gate-dielectric tunnel FET

Superlattices and Microstructures ◽

10.1016/j.spmi.2020.106748 ◽

2020 ◽

pp. 106748

Author(s):

Sarabjeet Kaur ◽

Ashish Raman ◽

Rakesh Kumar Sarin

Keyword(s):

Gate Dielectric ◽

Double Gate ◽

Capacitance Model ◽

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Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric

IEEE Transactions on Electron Devices ◽

10.1109/ted.2007.899389 ◽

2007 ◽

Vol 54 (7) ◽

pp. 1725-1733 ◽

Author(s):

Kathy Boucart ◽

Adrian Mihai Ionescu

Keyword(s):

Gate Dielectric ◽

Double Gate ◽

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Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric

Solid-State Electronics ◽

10.1016/j.sse.2007.09.014 ◽

2007 ◽

Vol 51 (11-12) ◽

pp. 1500-1507 ◽

Author(s):

Kathy Boucart ◽

Adrian Mihai Ionescu

Keyword(s):

Gate Dielectric ◽

Double Gate ◽

High K ◽

Length Scaling ◽

High K Gate Dielectric

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Double Gate Tunnel FET with ultrathin silicon body and high-k gate dielectric

2006 European Solid-State Device Research Conference ◽

10.1109/essder.2006.307718 ◽

2006 ◽

Author(s):

Kathy Boucart ◽

Adrian Ionescu

Keyword(s):

Gate Dielectric ◽

Double Gate ◽

High K ◽

High K Gate Dielectric

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A Physicsbased Model for Electrical Parameters of Double gate Hetero-material Nano Scale Tunnel FET

International Journal of Applied Information Systems ◽

10.5120/ijais12-450142 ◽

2012 ◽

Vol 1 (3) ◽

pp. 25-32 ◽

Author(s):

Brinda Bhowmick ◽

Srimanta Baishya

Keyword(s):

Double Gate ◽

Electrical Parameters ◽

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The impact of high-k gate dielectric on Junctionless Vertical Double Gate MOSFET

International Journal of Computer Sciences and Engineering ◽

10.26438/ijcse/v6i6.14751478 ◽

2018 ◽

Vol 6 (6) ◽

pp. 1475-1478

Author(s):

Jagdeep Rahul

Keyword(s):

Gate Dielectric ◽

Double Gate ◽

High K ◽

Double Gate Mosfet ◽

High K Gate Dielectric

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Investigation of Homo and Hetero-Junction Double-Gate Tunnel-FET-Based Adiabatic Inverter Circuits

IETE Journal of Research ◽

10.1080/03772063.2020.1859951 ◽

2020 ◽

pp. 1-9

Author(s):

M. Pown ◽

S. Sandeep ◽

B. Lakshmi

Keyword(s):

Double Gate ◽

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Semiconductor-Thickness-Dependent Design of Hetero-Gate Dielectric in Double-Gate TFETs

2020 IEEE Eighth International Conference on Communications and Electronics (ICCE) ◽

10.1109/icce48956.2021.9352038 ◽

2021 ◽

Author(s):

Nguyen Dang Chien ◽

Nguyen Van Hao ◽

Le Van Tung ◽

Chun-Hsing Shih

Keyword(s):

Gate Dielectric ◽

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Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits

2013 Annual International Conference on Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy ◽

10.1109/aicera-icmicr.2013.6575992 ◽

2013 ◽

Author(s):

Abhishek Mishra ◽

Manisha Pattanaik ◽

Varun Sharma

Keyword(s):

Logic Circuits ◽

Double Gate ◽

Hybrid Cmos ◽

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Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581) ◽

10.1145/383082.383136 ◽

2001 ◽

Author(s):

Rongtian Zhang ◽

Kaushik Roy ◽

David Janes

Keyword(s):

Low Power ◽

Circuit Design ◽

High Performance ◽

Double Gate ◽

Fully Depleted ◽

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