Placement of multiple dies on an MCM or high-performance VLSI substrate is a nontrivial
task in which multiple criteria need to be considered simultaneously to obtain a
true multi-objective optimization. Unfortunately, the exact physical attributes of a
design are not known in the placement step until the entire design process is carried out.
When the performance issues are considered, crosstalk noise constraints in the form
of net separation and via constraint become important. In this paper, for better
performance and wirability estimation during placement for MCMs, several performance
constraints are taken into account simultaneously. A graph-based wirability
estimation along with the Genetic placement optimization technique is proposed to
minimize crosstalk, crossings, wirelength and the number of layers. Our work is
significant since it is the first attempt at bringing the crosstalk and other performance
issues into the placement domain.
Deep-submicron Placement Minimizing Crosstalk