Estimation of crosstalk noise for RLC interconnects in deep submicron VLSI circuit

2015 ◽  
Author(s):  
Md. Maniruzzaman ◽  
Shakil Ahmed ◽  
Galib Md. Fattah ◽  
Rafia Nishat Toma
Keyword(s):  
Deep Submicron ◽  
Vlsi Circuit ◽  
Crosstalk Noise ◽  
Rlc Interconnects

Interconnect crosstalk noise evaluation in deep-submicron technologies

2009 ◽  
Vol 49 (2) ◽  
pp. 170-177 ◽  
Author(s):  
Xiaoxiao Liu ◽  
Guangsheng Ma ◽  
Jingbo Shao ◽  
Zhi Yang ◽  
Guanjun Wang
Keyword(s):  
Deep Submicron ◽  
Crosstalk Noise ◽  
Noise Evaluation

A New Spatial Correlation Model Based on the Distributed RC-∏ Model

2014 ◽  
Vol 989-994 ◽  
pp. 2204-2207
Author(s):  
Xiao Xiao Liu ◽  
Jing Bo Shao ◽  
Ling Ling Zhao
Keyword(s):  
Gaussian Process ◽  
Spatial Correlation ◽  
Process Variations ◽  
Deep Submicron ◽  
Correlation Model ◽  
Crosstalk Noise ◽  
Model Based ◽  
Reduction Techniques ◽  
Non Gaussian ◽  
Tree Branch

To solve the crosstalk noise question in deep-submicron technologies, a new spatial correlation model based on the distributed RC-π model is proposed in this paper. Quiet aggressor net and tree branch reduction techniques are introduced to the distributed RC-π model, and a new spatial correlation model of both Gaussian and non-Gaussian process variations among segments is created. Experimental results show that our method maintains the efficiency of past approaches, and significantly improves on their accuracy.

scholarly journals FDTD modeling for Crosstalk Reduction in Coupled RLC Interconnects with Active Shielding

2019 ◽  
Vol 8 (11) ◽  
pp. 1038-1042
Keyword(s):  
Crosstalk Noise ◽  
Delay Reduction ◽  
Proposed Model ◽  
Rlc Interconnects ◽  
Crosstalk Reduction ◽  
Global Interconnects ◽  
Active Shielding

This paper presents efficient geometry for crosstalk noise and delay reduction using Active shielding in RLC interconnects with resistive drivers .FDTD modeling has been used for proposed geometry and is validated by HSPICE simulations for 32nm global interconnects .From the results it has been verified that the proposed model results and HSPICE simulations differ by 5% . From the outcomes it has been confirmed that the proposed model outcomes and HSPICE outcomes differ by 5% and by using proposed geometry crosstalk noise and delay has come down by 73% and 60% when compared to unshielded line

scholarly journals Deep-submicron Placement Minimizing Crosstalk

VLSI Design ◽  
2001 ◽  
Vol 12 (1) ◽  
pp. 1-12
Author(s):  
Jun Dong Cho ◽  
Jin Youn Cho
Keyword(s):  
High Performance ◽  
Optimization Technique ◽  
Deep Submicron ◽  
Multi Objective Optimization ◽  
Crosstalk Noise ◽  
Performance Constraints ◽  
Placement Optimization ◽  
Number Of Layers ◽  
Physical Attributes ◽  
Performance Issues

Placement of multiple dies on an MCM or high-performance VLSI substrate is a nontrivial task in which multiple criteria need to be considered simultaneously to obtain a true multi-objective optimization. Unfortunately, the exact physical attributes of a design are not known in the placement step until the entire design process is carried out. When the performance issues are considered, crosstalk noise constraints in the form of net separation and via constraint become important. In this paper, for better performance and wirability estimation during placement for MCMs, several performance constraints are taken into account simultaneously. A graph-based wirability estimation along with the Genetic placement optimization technique is proposed to minimize crosstalk, crossings, wirelength and the number of layers. Our work is significant since it is the first attempt at bringing the crosstalk and other performance issues into the placement domain.

scholarly journals Energy Efficient Signaling in Deep-submicron Technology

VLSI Design ◽  
2002 ◽  
Vol 15 (3) ◽  
pp. 563-586 ◽  
Author(s):  
Imed Ben Dhaou ◽  
Keshab K. Parhi ◽  
Hannu Tenhunen
Keyword(s):  
Power Consumption ◽  
Energy Savings ◽  
Supply Voltage ◽  
Reducing Power ◽  
Deep Submicron ◽  
Experimental Results ◽  
Cmos Process ◽  
Buffer Insertion ◽  
Crosstalk Noise ◽  
Estimation Algorithms

In deep-submicron technology, global interconnect capacitances have started reaching several orders of magnitude greater than the intrinsic capacitances of the CMOS gates. The dynamic power consumption of a CMOS gate driving a global wire is the sum of the power dissipated due to (dis)charging (i) the intrinsic capacitance of the gate, and (ii) the wire capacitance. The latter is referred to as on-chip signaling power consumption. In this paper, a scheme has been proposed for combating crosstalk noise and reducing power consumption while driving the global wire at an optimal delay. This scheme is based on reduced voltage-swing signaling combined with buffer-insertion and resizing. The buffers are inserted and resized to compensate for the speed degradation caused by scaling the supply voltage and eradicating the crosstalk noise. A new buffer insertion algorithm called VIJIM has been described here, along with accurate delay and crosstalk-noise estimation algorithms for distributed RLC wires. The experimental results show that the VIJIM algorithm inserts fewer buffers into non-critical nets than does the existing buffer-insertion algorithms. In a 0.25 mm CMOS process, the experimental results show that energy savings of over 60% can be achived if the supply voltage is reduced from 2.5 to 1.5 V.

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