scholarly journals Energy Efficient Signaling in Deep-submicron Technology

VLSI Design ◽  
2002 ◽  
Vol 15 (3) ◽  
pp. 563-586 ◽  
Author(s):  
Imed Ben Dhaou ◽  
Keshab K. Parhi ◽  
Hannu Tenhunen
Keyword(s):  
Power Consumption ◽  
Energy Savings ◽  
Supply Voltage ◽  
Reducing Power ◽  
Deep Submicron ◽  
Experimental Results ◽  
Cmos Process ◽  
Buffer Insertion ◽  
Crosstalk Noise ◽  
Estimation Algorithms

In deep-submicron technology, global interconnect capacitances have started reaching several orders of magnitude greater than the intrinsic capacitances of the CMOS gates. The dynamic power consumption of a CMOS gate driving a global wire is the sum of the power dissipated due to (dis)charging (i) the intrinsic capacitance of the gate, and (ii) the wire capacitance. The latter is referred to as on-chip signaling power consumption. In this paper, a scheme has been proposed for combating crosstalk noise and reducing power consumption while driving the global wire at an optimal delay. This scheme is based on reduced voltage-swing signaling combined with buffer-insertion and resizing. The buffers are inserted and resized to compensate for the speed degradation caused by scaling the supply voltage and eradicating the crosstalk noise. A new buffer insertion algorithm called VIJIM has been described here, along with accurate delay and crosstalk-noise estimation algorithms for distributed RLC wires. The experimental results show that the VIJIM algorithm inserts fewer buffers into non-critical nets than does the existing buffer-insertion algorithms. In a 0.25 mm CMOS process, the experimental results show that energy savings of over 60% can be achived if the supply voltage is reduced from 2.5 to 1.5 V.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

Ground-Adjustable Inductor for Wide-Tuning VCO Design

2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Supply Voltage ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Wide Tuning Range ◽  
Chip Area ◽  
Ground Plate

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell

2015 ◽  
Vol 25 (01) ◽  
pp. 1640006
Author(s):  
Suyan Fan ◽  
Man-Kay Law ◽  
Mingzhong Li ◽  
Zhiyuan Chen ◽  
Chio-In Ieong ◽  
...  
Keyword(s):  
Solar Cell ◽  
Power Consumption ◽  
Supply Voltage ◽  
Capacitive Sensor ◽  
Cmos Process ◽  
Readout Circuit ◽  
Worst Case ◽  
Average Power Consumption ◽  
Input Range ◽  
On Chip

In this paper, a wide input range supply voltage tolerant capacitive sensor readout circuit using on-chip solar cell is presented. Based on capacitance controlled oscillators (CCOs) for ultra-low voltage/power consumption, the sensor readout circuit is directly powered by the on-chip solar cell to improve the overall system energy efficiency. An extended sensing range with high sensing accuracy is achieved using a two-step successive approximation register (SAR) and delta-sigma ([Formula: see text]) analog-to-digital (A/D) conversion (ADC) scheme. Digital controls are generated on-chip using a customized sub-threshold digital standard cell library. Systematic error analysis and optimization including the finite switch on-resistance, buffer input-dependent delay, and SAR quantization nonlinearity are also outlined. High power supply rejection ratio (PSRR) is ensured by using a pseudo-differential topology with ratiometric readout. The complete sensing system is implemented using a standard 0.18[Formula: see text][Formula: see text]m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the readout circuit achieves a wide input range from 1.5[Formula: see text]pF to 6.5[Formula: see text]pF with a worst case PSRR of 0.5% from 0.3[Formula: see text]V to 0.42[Formula: see text]V (0.67% from 0.3[Formula: see text]V to 0.6[Formula: see text]V). With a 3.5[Formula: see text]pF input capacitance and a 0.3[Formula: see text]V supply, the [Formula: see text] stage achieves a resolution of 7.1-bit (corresponding to a capacitance of 2.2[Formula: see text]fF/LSB) with a conversion frequency of 371[Formula: see text]Hz. With an average power consumption of 40[Formula: see text]nW and a sampling frequency of 47.5[Formula: see text]kHz, a figure-of-merit (FoM) of 0.78[Formula: see text]pJ/conv-step is achieved.

scholarly journals A Low Power Sigma-Delta Modulator with Hybrid Architecture

Sensors ◽  
2020 ◽  
Vol 20 (18) ◽  
pp. 5309
Author(s):  
Shengbiao An ◽  
Shuang Xia ◽  
Yue Ma ◽  
Arfan Ghani ◽  
Chan Hwang See ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Supply Voltage ◽  
Total Power ◽  
Cmos Process ◽  
Hybrid Architecture ◽  
Sigma Delta Modulator ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Total Power Consumption

Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

Integral Type Multi-Ramp for Single-Slope ADC

2013 ◽  
Vol 303-306 ◽  
pp. 1908-1912 ◽  
Author(s):  
Nan Lyu ◽  
Ning Mei Yu ◽  
He Jiu Zhang
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Supply Voltage ◽  
High Accuracy ◽  
Sampling Frequency ◽  
Cmos Process ◽  
Voltage Reference ◽  
Integral Type ◽  
Power Supply Voltage ◽  
The One

This paper presents a integral type Multi-ramp architecture apply to MRSS ADC (Multiple-ramp single-slope ADC).On the one hand to improve the capacitance mismatch by change voltage reference, On the other hand to reduced the power consumption greatly. Implemented in the GSMC 180nm 2P4M CMOS process, in the power supply voltage of 1.8 V, 11-bit resolution, 10 MHZ sampling frequency, the result of max power consumption is 1.33mW of single unit .The DNL < 0.1LSB and max INL < 0.49LSB .The Multi-ramp achieved requirements for high speed and high accuracy MRSS ADC.

Statistical Simulations on Perceptron-Based Adders

2011 ◽  
pp. 1474-1481
Author(s):  
Snorre Aunet ◽  
Hans Kristian Otnes Berge
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Reducing Power ◽  
Process Variations ◽  
Full Adder ◽  
Cmos Technology ◽  
Subthreshold Cmos ◽  
Order Of Magnitude ◽  
Supply Voltages ◽  
Circuit Technique

In this article we compare a number of full-adder (1- bit addition) cells regarding minimum supply voltage and yield, when taking statistical simulations into account. According to the ITRS Roadmap two of the most important challenges for future nanoelectronics design are reducing power consumption and increasing manufacturability (ITRS, 2005). We use subthreshold CMOS, which is regarded by many as the most promising ultra low power circuit technique. It is also shown that a minimum redundancyfactor as low as 2 is sufficient to make circuits maintain full functionality under the presence of defects. This is, to our knowledge, the lowest redundancy reported for comparable circuits, and builds on a method suggested a few years ago (Aunet & Hartmann, 2003). A standard Full-Adder (FA) and an FA based on perceptrons exploiting the “mirrored gate”, implemented in a standard 90 nm CMOS technology, are shown not to withstand statistical mismatch and process variations for supply voltages below 150 mV. Exploiting a redundancy scheme tolerating “open” faults, with gate-level redundancy and shorted outputs, shows that the same two FAs might produce adequate Sum and Carry outputs at the presence of a defect PMOS for supply voltages above 150 mV, for a redundancy factor of 2 (Aunet & Otnes Berge, 2007). Two additional perceptrons do not tolerate the process variations, according to simulations. Simulations suggest that the standard FA has the lowest power consumption. Power consumption varies more than an order of magnitude for all subthreshold FAs, due to the statistical variations

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