A single chip BiMOS telephone set

2003 ◽  
Author(s):  
C. Nguyen ◽  
P. Consiglio ◽  
F. Adduci ◽  
G.P. Vanalli ◽  
F. Marti ◽  
...  
Keyword(s):  
Single Chip ◽  
Telephone Set

A single chip telephone set

1983 ◽  
Author(s):  
W. Pace ◽  
R. Yarnold
Keyword(s):  
Single Chip ◽  
Telephone Set

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

Research on highly parallel embedded control system design and implementation method

Impact ◽  
2019 ◽  
Vol 2019 (10) ◽  
pp. 44-46
Author(s):  
Masato Edahiro ◽  
Masaki Gondo
Keyword(s):  
Computer Architecture ◽  
Intelligent Systems ◽  
Large Scale ◽  
General Purpose ◽  
Heterogeneous Structure ◽  
Single Chip ◽  
Powertrain Control ◽  
Processing Power ◽  
Hardware Description ◽  
Many Core

The pace of technology's advancements is ever-increasing and intelligent systems, such as those found in robots and vehicles, have become larger and more complex. These intelligent systems have a heterogeneous structure, comprising a mixture of modules such as artificial intelligence (AI) and powertrain control modules that facilitate large-scale numerical calculation and real-time periodic processing functions. Information technology expert Professor Masato Edahiro, from the Graduate School of Informatics at the Nagoya University in Japan, explains that concurrent advances in semiconductor research have led to the miniaturisation of semiconductors, allowing a greater number of processors to be mounted on a single chip, increasing potential processing power. 'In addition to general-purpose processors such as CPUs, a mixture of multiple types of accelerators such as GPGPU and FPGA has evolved, producing a more complex and heterogeneous computer architecture,' he says. Edahiro and his partners have been working on the eMBP, a model-based parallelizer (MBP) that offers a mapping system as an efficient way of automatically generating parallel code for multi- and many-core systems. This ensures that once the hardware description is written, eMBP can bridge the gap between software and hardware to ensure that not only is an efficient ecosystem achieved for hardware vendors, but the need for different software vendors to adapt code for their particular platforms is also eliminated.

scholarly journals Drink-driving monitoring system based on single chip microcomputer and sensor

2021 ◽  
Vol 1750 ◽  
pp. 012037
Author(s):  
Yong Chen ◽  
Shudong Wang ◽  
Hao Wang ◽  
Shen Liu ◽  
Runqing Li
Keyword(s):  
Monitoring System ◽  
Single Chip ◽  
Single Chip Microcomputer

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

scholarly journals Pixeled metasurface for multiwavelength detection of vitamin D

Nanophotonics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 3921-3930
Author(s):  
Valentina Di Meo ◽  
Alessio Crescitelli ◽  
Massimo Moccia ◽  
Annamaria Sandomenico ◽  
Angela M. Cusano ◽  
...  
Keyword(s):  
Vitamin D ◽  
Small Molecules ◽  
Vibrational Excitation ◽  
Localized Surface Plasmon ◽  
Large Field ◽  
Geometrical Parameters ◽  
Single Chip ◽  
Large Area ◽  
Accurate Analysis ◽  
Hydroxyvitamin D

AbstractThe steadily increasing demand for accurate analysis of vitamin D level, via measurement of its best general marker, 25-hydroxyvitamin D (25(OH)D), pushes for the development of novel automated assays capable of working at very low concentrations. Here, we propose a plasmonic biosensor of 25(OH)D3 (calcifediol) based on surface-enhanced infrared absorption spectroscopy, which exploits the resonant coupling between plasmonic nanoantennas and vibrational excitation of small molecules. Specifically, our proposed platform features a large-area (several mm2) metasurface made of gold nanoantennas fabricated on a silicon substrate, comprising different macroregions (“pixels”) of area 500 × 500 µm2. In each pixel, the nanoantenna geometrical parameters are tuned so as to support localized surface plasmon resonances (and hence large field enhancements at the nanoscale) within different regions of the infrared spectrum. As a result, a single chip is capable of performing analysis from the region of functional groups to that of fingerprint. Two different designs are fabricated via electron beam lithography, functionalized with a correlated antibody for the detection of 25(OH)D3, and characterized via Fourier-transform infrared spectroscopy. Our experiments demonstrate the capability to detect a concentration as low as 86 pmol/L, and an amount of immobilized small molecules of 25(OH)D3 monohydrate (molecular weight: 418.65 g/mol) as low as 4.31 amol over an area of 100 × 100 µm2.

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